AMD: Pirate Islands (R* 3** series) Speculation/Rumor Thread

I know, just poking fun. First/quick glance it looked funny (especially upside-down).

 

This is water cooled right?

 

Nearly 100% sure that the "official" version will be effectively watercooled, im too 100% sure that, Sapphire, Asus etc will have air cooled version.

It do even more sense for watercooling with HBM on the same package of the core. Only thing left to cool will be the PWM circuit.

Custom waterblock from EK and other brands will be a really funny pieces with high performance, less routing for the water, higher flow. When i look my full cover GPU's waterblocks from EK, i easely see where the gain will come.

 

Intel's EMIB works along those lines, where there are small bridges of high-density interconnect embedded in a package. The bridge does not need to be silicon, and if it is silicon it doesn't need vias drilled through it since it is no longer responsible for non-interconnect.

http://www.intel.com/content/www/us/en/foundry/emib.html

Intel has a history of good packaging tech that it can produce affordably, which other vendors may have difficulty matching.
The package is more complex, and having independent interposers means extra work making sure alignment across physically unconnected chips is handled well.
IBM has a history of high-end packaging, but that's a price tier beyond mere mortals.

It's possible that the foundries are more comfortable with the interposer tech because it is a straightforward move from the chip fabbing they already do.
Another possibility is to fab large interposers with specific areas that have the highest-density interconnect, where the finest connections do not cross from one sector to the other. This does not save silicon, but it is an area where there are existing techniques of working around the reticle that the vendors would be familiar with.

One hypothetical reason why AMD might want to keep that silicon is that the interposer doesn't necessarily need to only provide connections solely at the periphery of a large chip and memory. There is research that may very well not come to anything where the higher wiring density can be used to create an additional network on the package, although the proposal relies on bump pitches finer than HBM does.
http://www.eecg.toronto.edu/~enright/micro14-interposer.pdf

There are mounting methods with much finer pitches, but it's not clear they can work in this situation, or do so affordably.

Other presentations concerning the dis-integration of dies, modularization for custom designs, and AMD's loss of coarser metal layers from its CPU processes show there could be a use for it, although whether it can be made practical is a separate question.

 

Well, now I'm shocked by how much interposer is "going to waste". Dare say it looks more like 19 x 22mm. Error margin in die area is well over 10%, I suppose, which is arguably more than the area that might be saved in PHY going from GDDR5 to HBM

Maybe it's some sort of RV770 like magic that they manage to cram so much performance into a die that's about the same size as Hawaii. (Tonga, against Tahiti perhaps, is indicative of gains in transistor density per mm² - some of which would be helped though by Tonga's smaller and slower GDDR5 bus.)

EDIT: pixel counting on this image indicates to me that the "height" of the interposer featured there is only 23mm. This is based on the 107 pixel length of the HBM, which is 7.3mm. The GPU height appears to be 21mm.

2nd EDIT: (sorry, got distracted by a 918 v P1 argument), if the interposer is 32mm wide, then the GPU can be 20mm. Widthwise, the distance from GPU edge to interposer edge appears to be precisely 6mm.

So as far as I can tell, Fiji is no more than 21 x 20mm = 420mm².

 

Is it? It's about as large, and a bit slower. Granted, with the remaining CUs enabled it would probably be faster, but it's a fairly marginal improvement (unless it also has disabled memory controllers of course).

 

I was talking about the transistor density. There's something like 700 million more transistors in there.

It seems to be faster than Tahiti in Witcher 3

Hairworks, apprehensions about closed source libraries proven beyond reasonable doubt?

 

AMD suggests one to turn down the tessellation to make it run faster on all Radeons, 16x was IIRC virtually indistinguishable from the default 64x, but performance was notably better.

 

Thoses benchmark are without hairwork. just for said.

 

285 was doing better than 7970Ghz. However those benches are without hairworks, with them 285 falls behind 280X from the other becnhmarks I have seen. Certainly strange if the tessellation is the prime culprit.

 

Yes, but on average it's slower. Perhaps that trend will reverse with future games, if they put more stress on the front-end.

 

It's weird really. In Tessmark (OpenGL) Tonga is 2x faster than Tahiti, while the synthetic geometry benches from Hardware.fr point to a conclusion that Tonga is no faster during primitive rasterization.

 

@repi Got his hands on Pirate Islands

https://twitter.com/repi/status/601739457960763392

 

https://forum.beyond3d.com/threads/...ation-rumor-thread.55600/page-53#post-1845148

 

Post was not visible to me. My bad.

 

This is your first infraction, so I shall forgive you! But ye shall never do it again

 

@repi AMD won't give you shit for tweeting that image?

 

The tweet said it was a sweet GPU.
The card's enclosure and general fit and finish indicate the shroud and heatsink assembly are intact.

I cannot give credence to that claim, when it is obvious he has not licked the GPU.

 

Does that mean I can claim it if I find it? I mean, it's cootie free right now so...

 

It isn't obvious to me at all. Consider that if the GPU had been coated in sugar prior to shipping, the heat it generated whilst rendering frostbite 4 test scenes at bajillions of fps would have transformed the sugar into caramel, at which point one would have to be forgiven for scrupulously licking its entire surface back into a spotless state.