AMD: Pirate Islands (R* 3** series) Speculation/Rumor Thread

It's disappointing that the article didn't have the courage to stake a claim as to how this would occur.
Is it saying HBM2 is something Fiji or a revision could support?
Is it saying Fiji is shipping with half its memory bus and controllers unused because of reasons (available interposers not up to what the big solution needs, costs not there, designer sent specs to manufacturing in a GIF and accidentally cropped half the chip out, drugs?).
Where's the flight of fancy into assuming clamshell mode could apply, or a secret HBM 1.5 revision?
 
I never really understood why HBM 1.0 should be limited to 1GB per stack. It seems like something that should be purely a function of density, and independent of the revision.
 
How weird/hard would it be to have two distinct memory pools, 4GB HBM and 4GB GDDR5 (in a 128bit bus, for example)?

Even if both pools would have different bandwidths, nVidia has made at least 2 graphics cards using memory banks with uneven performance: GK104 in 660 Ti and GM104 in GTX 970.

It just seems to me that 4GB will be too much of a limitation for the performance these cards are rumoured to have.
 
ToTTenTranz said:
How weird/hard would it be to have two distinct memory pools, 4GB HBM and 4GB GDDR5 (in a 128bit bus, for example)?

Even if both pools would have different bandwidths, nVidia has made at least 2 graphics cards using memory banks with uneven performance: GK104 in 660 Ti and GM104 in GTX 970.

It just seems to me that 4GB will be too much of a limitation for the performance these cards are rumoured to have.
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Like XB1 on-chip ESRAM (4 channels x 256bit = 1024 bit) and off-chip DDR3 (4 channels x 64bit = 256bit) !
 
Alexko said:
I never really understood why HBM 1.0 should be limited to 1GB per stack. It seems like something that should be purely a function of density, and independent of the revision.
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I don't think HBM1 tech itself would prevent using 4Gb density chips for example, but it's better to go safe on new standard I suppose?
 
sebbbi said:
IMHO, it is only a matter of time when we get these to DirectX, since the cross lane operations provide nice performance gains for many algorithms (reduced GPR usage, reduced LDS usage, less instructions, etc) and at the same time make writing these algorithms much simpler.
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Your words in MS's ears. I really hope so as well, but I got not much faith. :-| Maybe I'll try to hack Gallium to drown my sadness. :D
 
I can't wait anymore for R300, so in effort to make my PC gaming-ready I ordered factory overclocked second hand 270X. Hopefully by the summer AMD will not only introduce great performance chips, but will also slash prices of Nvidia offerings.
 
http://videocardz.com/55124/amd-radeon-r9-390x-wce-could-this-be-real
Intersting if true
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Would mean Hynix has after all done HBM's with 4Gb density DRAM chips even though their own 1st gen HBM specs don't seem to mention such possibility

One point though, note that the slide is dated for tomorrow (16th), could be that it's gonna be sent to us media tomorrow but could just point it being fake too
 
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