AMD: Pirate Islands (R* 3** series) Speculation/Rumor Thread

Wasn't this exact same VR demo used by Nvidia months ago on a gtx 980? Running at 90fps no less.

Why bother even showing up to this event if all your going to do is hide the hardware and show off software demos that can be run on competitor hardware. This a low budget even for AMD standards.
 
Entropy said:
What bothers me a bit with the release schedule and approximate availability of this flagship product is that it may indicate that new lithographic technique may be further out into the future than I had assumed. I don't know how long the 390 needs to be on the market in a flagship capacity to be meaningful, though. Maybe not all that long.
But if AMD wants to compete at all for laptop or Apple contracts, they need to provide good performance/watt and staying around on 28nm won't do when they are competing with Skylake and nVidia. On the other hand, it is clearly a flagship desktop product, so maybe it doesn't say much about when AMD will move other product segments to lower power process technology.
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Well, NVIDIA is kind of giving away Apple contracts on a platter to AMD because of their slow OpenCL support.
 
sheepdogexpress said:
Wasn't this exact same VR demo used by Nvidia months ago on a gtx 980? Running at 90fps no less.

Why bother even showing up to this event if all your going to do is hide the hardware and show off software demos that can be run on competitor hardware. This a low budget even for AMD standards.
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The point was to demonstrate LiquidVR, not demonstrate hardware. ( well aside that it was running with on AMD hardware ( next gpu ).

As AMD have team with Occulus , for what i have understand showdown is one of their demonstration set ( made by Epic at the demand of Occulus), dont be surprised to see it used .
 
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LordEC911 said:
Just want to clarify, the kitguru article specifically mentions a "family line-up" doesn't mean cards can't launch before hand. There are also multiple sources stating that there aren't going to be many rebrands.
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I agree. Similar to the 7000 series, I can see Fiji (paper) launching in April, limited availability in May with the rest of the rebrands and full Tonga showing up at Computex.
 
sheepdogexpress said:
Why bother even showing up to this event if all your going to do is hide the hardware and show off software demos that can be run on competitor hardware. This a low budget even for AMD standards.
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AFAIK There is exposure of LiquidVR has exposure of hardware (ACE's) that NVIDIA doesn't have an equivalent to at the moment.
 
Pressure said:
Well, NVIDIA is kind of giving away Apple contracts on a platter to AMD because of their slow OpenCL support.
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Doesn't stop Apple from offering nVidia graphics in their top of the line MacBook Pro, or in their non-retina iMacs. Just as I wouldn't say it's a non-issue, I don't think it is the only deciding factor either. When it comes to Apple, I really believe it would help AMD a lot to achieve better performance/power ratios. Moving to finer pitch FinFet will help a lot with that, as will new memory technology and architectural enhancements. It just has to happen in a timely manner for competitive reasons.
The Retina iMac contracts for instance has to be pretty attractive to get, and given the massive resolution of the screen (and Apples render-up-scale-down methods), it is a platform that will need discrete graphics for quite some time to come.
 
http://wccftech.com/xfx-radeon-r9-3...gddr5-vram-launches-april-2015/#ixzz3U4TxXZhL

TPbO5Pt.jpg




Pitcairn's R9 270X length was ~228mm, Tahiti's 280X is 300mm long and Tonga's 285 is 264mm.

167mm is really compact and Sapphire actually has a Tonga card with a similar length (171mm):
WFJBtZf.jpg

However, this one seems to need only one 6pin connector whereas all Tonga cards needed 2x6pin.

It doesn't seem like this card is another rebrand, like some have suggested.


Another thing: card description says 4GB, but GDDR5 amount is 2GB.
Perhaps 2GB GDDR5 + 2GB HBM?
EDIT: nevermind, the screenshot shows two different cards, the one on top is 2GB and the one on the bottom is 4GB.
 
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LordEC911 said:
Definitely will see stuff before June.

Supposed GCN Gen 3 documentation that was just released but it has a VI diagram...
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Since it's highly unlikely that a forum troll decided to write a fake 354-page document full of technical specifications, I think it's safe to drop the "supposed" qualifier. Has anyone perused it and noticed anything interesting?

That said, Tahiti was GCN, Bonaire was the second generation, so Tonga would logically be the third one.
 
Maybe this is me being awfully ignorant, but page 2-4 mentions a memory crossbar.
I thought that, within GCN, only Tahiti (so far) had a crossbar due to mismatched ROPs to memory channels.
 
Alexko said:
Since it's highly unlikely that a forum troll decided to write a fake 354-page document full of technical specifications, I think it's safe to drop the "supposed" qualifier.
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It'd be cool if it were fake, though. Just the thought. :)

Has anyone perused it and noticed anything interesting?
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Page XV lists the differences. Seems very much evolutionary. Mostly compute related?
 
The 16bit VALU instructions are kind of boring. Just using the low 16bit bits. So all the same throughput as the 32bit versions, though presumably saving power.
 
Dave Baumann said:
AFAIK, and register space. Performance improvement happen when there is register pressure.
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So you can confirm that GCN3 (apparently that's what it's called) can actually store two 16-bit values in a 32-bit register? This was unclear until now, and I think it was Sebbi who mentioned that if it were the case, it could make a big difference.
 
Dave Baumann said:
AFAIK, and register space. Performance improvement happen when there is register pressure.
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Oh I missed that. I just saw things like VOP2 v_add_f16 saying "d.f16 = s0.f16 + s1.f16". Assuming it's just fixed bits.
On a closer look however, there's VOP_SDWA (second dword for vop1/vop2/vopc instructions) which can swap bytes and words in inputs as well as destination. I guess that should do the trick. Presumably doesn't work for 3-source instructions however (most prominent probably being mad/fma) which is a pity.

edit: of course even without such sub-dword addressing it would still be possible to save registers. Just not looking that nice if you have to separately unpack and pack them always.
 
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As an aside, if this is a definitive document on the changes for GCN 3(?), could some clarity be provided on why the shared memory hierarchy diagram appears more appropriate for the Northern Islands ISA document rather than Southern Islands?
 
That picture is the same as featured in the Sea Islands ISA document. A very similar picture appears in the Southern Islands document, too.
 
The memory hierarchy in the currently hosted Southern Islands ISA doc labels the L1 and L2 as read/write. It calls the hardware units CUs, lists 64KB of LDS per CU, shows the SALU, has 4 SIMDs per CU, and shows 256x32 registers per VALU.

Figure 2.1 in the successive ISA docs reverts to the color scheme of AMD's Northern Islands documentation, reverts to the read cache labeling, does not have CUs, lists 32KB per SIMD, lists 256 128-bit registers per processor, and lists out the export buffer and write combining path that Southern Islands removed.

I do not recall any of that being valid for GCN, or consistent with other parts of the document.
 
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