IIRC it's the "Apple chip" aka Vega with 20 CUs40CU being the first navi chip as well, certainly looks like they had a decent source. I didn't pay much attention to that single shader engine chip, any pointers?
IIRC it's the "Apple chip" aka Vega with 20 CUs40CU being the first navi chip as well, certainly looks like they had a decent source. I didn't pay much attention to that single shader engine chip, any pointers?
Sure, but did anyone ever try to identify and label out the functional blocks in a Compute Unit on the actual die shot? Things like LDS/registers/TMUs etc.there is some risk in using an conceptual diagram to guess at physical dimensions
http://chipsleuth.com/tahiti.html#annotated-rams-overviewSure, but did anyone ever try to identify and label out the functional blocks in a Compute Unit on the actual die shot? Things like LDS/registers/TMUs etc.
Looks almost impossible to me without some inside information, since logic blocks are spread across all silicon-copper layers to maintain power and thermal limits, and the visible layer only reveals parts of these blocks but there is probably not enough information to reconstruct the entire CU .
The single official photo of a GCN die I could find is a functional diagram in the AMD Polaris whitepaper, with a grid of superimposed green squares standing in for CUs, but these don't even try to match the real Polaris10 die - though it does match what's visible of the real silicon like memory channels and I/O (for the most part, as the right edge is differrent).
with undervolt to 0.966V the card consumes slightly above 130W while clocking 40MHz lower.
That's sure interesting, even though the top layer only hosts SRAM in each CU.
I've seen various attempts over the years (including the site linked in a later post). I think reverse-engineering companies like Chipworks (now part of Techinsights?) would have more certain breakdowns--but those don't come cheap.Sure, but did anyone ever try to identify and label out the functional blocks in a Compute Unit on the actual die shot? Things like LDS/registers/TMUs etc.
Generally a unit of some kind is going to try to have a relatively contiguous 2D footprint (don't want more distance for signal travel if not necessary), although with automated synthesis the exact boundaries get pretty blobby. There's only one layer of active transistors, with the rest being interconnect and elements like power planes and inductors/capacitors. While there are concepts with more than one transistor layer, at least traditionally the electrical properties of layers besides the single layer that was cut from the mono-crystaline ingot have been too poor to be justified with most chips and workflows.Looks almost impossible to me without some inside information, since logic blocks are spread across all silicon-copper layers to maintain power and thermal limits, and the visible layer only reveals parts of these blocks but there is probably not enough information to reconstruct the entire CU .
As long as the die is roughly at the center between the mounting screws, I cannot understand how a heatsink's contact area would not make full contact with a smaller die than it was designed for. Contrarily, there would be a larger margin for error on the sides.My main concern with custom cooled cards is whether the heatsink/heatpipes make full contact with the die and aren't just carry-overs designed for nvidias larger dies.
Classic bad example: https://www.computerbase.de/2013-12/asus-radeon-r9-290x-directcu-ii-oc-test/2/#abschnitt_der_kuehlerAs long as the die is roughly at the center between the mounting screws, I cannot understand how a heatsink's contact area would not make full contact with a smaller die than it was designed for. Contrarily, there would be a larger margin for error on the sides.