AMD: Navi Speculation, Rumours and Discussion [2019-2020]

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http://www.freepatentsonline.com/10353591.html
Fused shader programs
Document Type and Number:
United States Patent 1035359
Assignee:
Advanced Micro Devices, Inc. (Sunnyvale, CA, US)

Abstract:
Improvements in compute shader programs executed on parallel processing hardware are disclosed. An application or other entity defines a sequence of shader programs to execute. Each shader program defines inputs and outputs which would, if unmodified, execute as loads and stores to a general purpose memory, incurring high latency. A compiler combines the shader programs into groups that can operate in a lower-latency, but lower-capacity local data store memory. The boundaries of these combined shader programs are defined by several aspects including where memory barrier operations are to execute, whether combinations of shader programs can execute using only the local data store and not the global memory (except for initial reads and writes) and other aspects.
 
AlBran said:
I'm partial to identifying Navi CUs as D(ouble) CUs.
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that is only partially true, because they can work together as workgroup or they can work independently....

861-cu-diagram.jpg
 
PizzaKoma said:
https://twitter.com/x/status/1155337190047723520

Probably for RDNA2 HPC chip or Arcturus? Uncertain about which thread this belongs in...
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HMC is pretty much a dead technology .... too expensive and too complicated

Last week, Micron announced a change in its strategy for high-performance memory solutions, moving away from Hybrid Memory Cube (HMC) and focusing on the next-generation of high-performance compute and networking solutions.
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https://www.micron.com/about/blog/2...t-in-high-performance-memory-roadmap-strategy
 
Kaotik said:
It's actually just about stacked memory, I'm pretty sure it makes no mentions of which specific type of memory would be used and quick scanning shows nothing related to HMC/Hybrid Memory Cubes
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Hmm? From the Micron Blog post by Andreas Schlapka (director of network technology in Micron's Compute and Networking Business Unit).

Last week, Micron announced a change in its strategy for high-performance memory solutions, moving away from Hybrid Memory Cube (HMC) and focusing on the next-generation of high-performance compute and networking solutions.
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And...

We continue to leverage our successful Graphics memory product line (GDDR) beyond the traditional graphics market and for extreme performance applications, Micron is investing in HBM (High-Bandwidth Memory) development programs which we recently made public.
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So it would appear that Micron is moving away from HMC and investing more into HBM.

I'd imagine existing customers could still get HBC, and if there was interest from a large player they might still make it for a new customer. But it sounds like they aren't putting any more R&D into it.

Regards,
SB
 
Silent_Buddha said:
Hmm? From the Micron Blog post by Andreas Schlapka (director of network technology in Micron's Compute and Networking Business Unit).



And...



So it would appear that Micron is moving away from HMC and investing more into HBM.

I'd imagine existing customers could still get HBC, and if there was interest from a large player they might still make it for a new customer. But it sounds like they aren't putting any more R&D into it.

Regards,
SB
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The "it" in my post was referring to the patent mentioned above, sorry for the confusion. I'm fully aware that HMC is dead and has been dead for some time
 
PizzaKoma said:
https://twitter.com/x/status/1155337190047723520

Probably for RDNA2 HPC chip or Arcturus? Uncertain about which thread this belongs in...
Click to expand...
As noted later, the claims don't discuss HMC. The method does sub-divide the stacked DRAM into vertical sections above a controller in a manner similar to HMC, but the memory interfaces with a GPU more like a form of LDS or distributed GDS.
If a memory segment is above the CU requesting data, the data is fed vertically down directly to the register file, which is closer to how the LDS might work versus the vector cache hierarchy. If the memory is not above a local CU, there's a potentially separate mesh of cached interface stops that pass data to the requester.

This patent came up earlier in the current thread: https://forum.beyond3d.com/posts/2075654/

Whether this is going into any product like Arcturus or incoming GFX10 chips, there are some signs that it is less likely.
For the GFX10 case, the claims discuss a SIMD16 GPU as an example that doesn't exclude a SIMD32 RDNA, but doesn't provide evidence for it being used either.
For Arcturus, the code commits that mention it include hints that it's likely to be running near the thermal limits of GCN's power management (power scheduling is explicitly disabled, compiler code is notified to avoid certain instruction mixes to avoid throttling), and there's mention of it being associated with the name MI-100. If the existing 7nm Instinct chips serve as a starting point for extrapolation, this seems like it runs too hot for a 3D stack. Earlier presentations on TOP-PIM gave a power ceiling of ~15W for memory and the silicon below it.
While there could be code changes in the future, neither GFX10 or Arcturus mention changes for a memory pool whose behavior may be very different from existing types. Vector memory in particular would have different rules, and I'm not sure the LDS/GDS changes indicate MB or GB of storage being made available.

On top of all this, I noted the first time around that this comes from a Department of Energy research program into HPC, which going by the history of other such patents from DOE programs has either a low chance of being used or a long timeline for being seen. Some of the low-voltage and variable-SIMD patents that people were clamoring about in 2016 (filed in 2014) as possibly being Vega or Navi-related have not shown up for either three years later, so if the trend persists it won't be applicable to any chip currently in the rumors for the near or mid-term.
 
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