AMD: Navi Speculation, Rumours and Discussion [2019-2020]

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The 5700 being made from a cut down Navi10 die, does this indirectly indicate that perhaps yields are so good they arnt concerned about defective dies, or is it more likely they have a stockpile of full Navi10 dies that will be used for the next few months?
 
DDH said:
The 5700 being made from a cut down Navi10 die, does this indirectly indicate that perhaps yields are so good they arnt concerned about defective dies, or is it more likely they have a stockpile of full Navi10 dies that will be used for the next few months?
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Probably means there's already enough inventory in the channel. It's not like Navi is a hot seller.
 
DDH said:
The 5700 being made from a cut down Navi10 die, does this indirectly indicate that perhaps yields are so good they arnt concerned about defective dies, or is it more likely they have a stockpile of full Navi10 dies that will be used for the next few months?
Click to expand...
5600XT is made from a cut down Navi 10 die too and should arguably be a much better seller than 5700XT.
They will probably drop 5700XT down in price after Navi 21 launch which won't leave any room for 5700 in between.
 
The cut down Navi 22 should be about as fast a 5700XT if the leaked specs are true and the Navi 23 specs looks a lot faster than the 5500XT so I don't see much room for Navi 10 left in the product stack if AMD does launch the full line.
 
SimBy said:
Techtuber that shall not be named says 29x18.5mm for N21. Take it with traversal co-processor amount of salt.
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Do you mean that one who stated that "Big Navi is not so big" (he said below 500mm² ) and now he came with this?

obrzek_2020-10-04_1111kk43.png
 
One might say the logic behind die size doesn't really matter. Fiji vs Vega 10 - the same core config besides memory - die size 596mm2 vs 495mm2 (120%) - process 28nm vs 14nm.
 
Jawed said:
Navi 10 with 160 CUs would be about that size (10240 ALU lanes), with 4 shader engines using up about 389mm². So one could ask, why did AMD not go with 160 CUs?
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Because then they'd need a gigantic bandwidth to feed those, and/or 160CUs would generate a tremendous amount of heat on 7nm?


CarstenS said:
New I. Like. Big. Dies andicannnot lie. *SCNR*
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Say no more fam.

JrrzXAO.jpg
 
yuri said:
One might say the logic behind die size doesn't really matter. Fiji vs Vega 10 - the same core config besides memory - die size 596mm2 vs 495mm2 (120%) - process 28nm vs 14nm.
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We are just trying to make sense of why it's so much bigger than XSX. There are only three options. Massive cache is real, die size is wrong, it's more than 80CUs.
 
I'm starting to suspect that AMD pulled off another RV770 feat, and that there are >80 CUs. Maybe something like 120? Sort of like how RV770 had 800 SPs instead of anticipated 640.
 
ToTTenTranz said:
Because then they'd need a gigantic bandwidth to feed those,
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Or lowered latency and better cache-hit rate of memory operations. Every cache miss wastes bandwidth compared with what would have happened with a larger cache.

and/or 160CUs would generate a tremendous amount of heat on 7nm?
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More heat than GA102? 536 versus 628mm²

Less ALU lanes than 3090?

Real world GPU clock of, say, 2100MHz versus 1950MHz?
 
I think we will se a dual PS5 GPU:


Maybe Xbox and PS5 are more different in CU than we thougt? I think for PS5 a lots of Transistors are going into Cache and to reache 2.23 GHz, the same like RDNA 2
Also we will see paradigm shift. If Mike Cernys words are true we will see more small polygons which make the layout for less/slow Rasterizer with much CU lead to an inbalance in the workload.


 
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