AMD: Navi Speculation, Rumours and Discussion [2019-2020]

I am so far surprised of the PS5 RT capabilities, still wondering if the SRAM in IO complex is the so called infinity cache. Would explain why they went with a 448 GB/s bandwidth.

 

I am also pretty surprised. However, to be fair to the general discussion, we've had little to no other way to compare nvidia results except to itself. Our understanding of what can be done with RT and what to expect from RT performance has largely been guided by Nvidia's hand here. Once RNDA 2 is out and both consoles are out pushing boundaries, we can get a better idea of what we can actually expect from RT.

 

@Love_In_Rio
@iroboto
I think the excellent RT we have seen so far on a few PS5 games could be mostly explained because of easy and mature APIs. Sony have being thinking about RT since at least 2013 as Cerny was already considering it for PS4 (but couldn't do it because of how expensive it was).

 

Every business have the goal to maximize revenue. is the same for AMD or even more considering it's smaller size. If Nvidia didn't use TSMC is because they couldn't that is sure of. and this " infinity cache" would probably allow them to safe a lot in the cost of PCB design and manufacture, that would reduce at least the impact in the price of die. We will see in a month what is the final product is.

You completely missed my point

 

He failed to notice they have the fastest GPUs out there, probably even comparing to RDNA2 in raw rasterization performance. Then we have all the other advanced features like ray tracing, dlss etc. All the while they came down in price and adding RTX IO, which is better specced then the PS5s solution.

I wont complain, only very intresting in what AMD will do, looks very promising so far. This competition is very much needed. AMD is on a roll with Zen3 leaving Zen2 in the dust.

 

Hbcc started with Vega, not Fiji... ?

 

Yes and no. Large caches were large consumers when transistor leakage current was a major problem, but finfets can push leakage really low, leaving only the active switching as the energy cost, and the only part of a cache that switches any given clock is the part that is accessed, and the access path. As caches grow in size, their energy consumption is almost flat. So while caches consume a lot, making caches larger makes them consume less per area. Improving hit rate of course increases energy consumption (as cache is effectively hit and therefore accessed more often), but linearly increasing cache size doesn't linearly increase hit rate. So again you are winning on power per area.

 

And you know that because...?. Get ready for a surprise.

 

While dynamic leakage is getting lower, static leakage is growing with each generation and growing caches. Fortunately it still looks like the dynamic power advantage outweighs the static leakage cost - at least in conventional high perf devices, battery powered devices have to use more aggressive power gating techniques on idle hardware.

 

Started and ended?

 

Do we have any specs on DirectStorage yet?

 

AFAICR, no RDNA products have every mentioned it. Also I don't believe Direct Storage is the same technology as HBCC, with the latter being attached storage that is directly memory addressable.

 

Sure, but it extends beyond DirectStorage in that it can be used as directly assigned VRAM. I don't believe there's been anything to indicate DS has that capability.

 

https://videocardz.com/newz/amd-radeon-rx-5700-series-reach-end-of-life

 

5700 vanilla only, per edit.