DegustatoR
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Or in the other dimension.
AMD: Navi Speculation, Rumours and Discussion [2019-2020]
- Thread starter Kaotik
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The only people bragging aren't AMD
?
Sorry I'm not following along.
How does screen tiled colour depth units (dramatically) lower the need for bandwidth (over the traditional RBE)
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a lot of lower precision ones with a couple higher precision ones. Some titles requiring up to 50+ various targets per frame.
Nvidia DLSS antialiasing discussion *spawn*
20ms is noted here. And thats on tensor cores, which AMD lacks.
A1xLLcqAgt0qc2RyMz0y
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Jawed
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How many of those are concurrently being written?
What exactly are we suppose to conclude from this when we don't know which RDNA2 based GPU this is? And we know there are probably at least 4 SKUs. 2 based on N21 and two based on N22.
Hmm. I don’t know if it matters. I think what matters is how much fill-rate you require to complete the full frame. I don’t think games will usually max out full rate for the whole second.
isn't the 3070 supposed to be that fast also ?
nice! Since I am not in a hurry to decide my future graphics card since the 1080 is performing okay as of currently, this info has been the most valuable for now regarding AMD.
I am still missing a DLSS like solution, but something like the per watt performance seems to be improved a lot and given the fact that I want to play all games at 165fps 1440p native, and I have a limited power budget -550W PSU, yeah I thought about it before buying it and knew what I wanted-, things are getting more interesting by the day.
Rootax
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Yeah, not in a hurry either, my watercooled vega fe is doing the job fine for now. I don't play fast fps, so being 40+ fps, high/max detail, for my rpg / adventure games, is ok to me, I've a freesync monitor, it's all right (...and I've bought a new car, and planning a Pixel 5 and a PS5, so I don't have money anymore
).I just want competition
It's supposedly not N21 but N22, but who knows, it's wild west out there.
another reason amd should have planned for an earlier announcement. Now its just almost 2 months of rumors and the majority seem to be negative.
Love_In_Rio
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Hasnt XSX APU 76 MB of ESRAM nobody has cleared where comes from?.
Unknown at this time, but AMD's hybrid RT patent has the SIMD pass a BVH pointer and ray origin and direction data to the hardware in the texture block. The RT hardware returns a payload containing intersection test results and pointers to the next set of BVH nodes.
Whatever node payload and filtering of the BVH nodes being requested in the current iteration seems to be loaded and calculated by the RT block.
Microsoft has used its own particular wording for hardware blocks before, going by its naming convention for compute units in the current gen. The coloration of the color/depth blocks is also green versus the blue cache blocks in the diagram. Seems like an omission to not note a 128MB collection next to the 4MB L2, for example. As great as it might be to have a massive frame buffer on-die, it seems like something could be done to make more use of it than closing the ROP memory loop on-die. For example, the geometry engine and binning rasterizers would likely have a decent idea of how many screen tiles may be reasonably needed in a given time window, and that could leave much of that cache available for something other than ROP exports.
The "infinity cache" name may also hint at an arrangement where it's in or near the data fabric, outside of the L2 and outside the scope of the diagram.
However, the probable die area cost might have discouraged the cost-sensitive vendors from adopting something like this.
While the large cache concept has some difficulties that haven't been resolved, let's stipulate that it exists for the sake of continuing the argument for some kind of hybrid memory controller setup or chiplets. One possible way to have the necessary area is to have a cache layer inside of an active interposer containing the memory controllers and a fabric network.
That wouldn't crowd the logic above, and it might be more amenable to the thermal conditions below an active die and the disruption due to TSVs.
Such a GPU would also not be constrained to a single memory controller type, since it would be hosted by the interposer. Software may reference both modes of operation if an interposer can support both, or if the same GPU can be mounted on different interposers. An APU with integrated memory controllers like the consoles wouldn't have a memory controller die with its cache, or possibly the cost of such a thing is why the consoles remain fully integrated.
A high-end GPU might have the margin and lower volumes that don't exceed the capacity of the integration process for mass production.
The context seems to be that the cache is meant to make up for not having an extremely wide GDDR6 bus or HBM. A more modest GPU might be low enough to be satisfied with regular GDDR6 bus without incurring a significant die cost that a console may not be able to justify.
If there were some kind of advanced integration necessary, that might lead to such a thing being ruled out.
The comparison I was thinking of was between a more conventional hierarchy and one with a 128MB additive cache layer.
If the RT workload is random enough and more sensitive to round-trip latency, the RT blocks could see limited upside.
GCN's L1 hit latency is ~114 cycles, L2 is ~190, and an L2 miss ~350, per a GDC2018 presentation on graphics optimization.
RDNA has another layer of cache, although the exact latencies aren't clear. A ~10% improvement in overall latency was mooted, but attributed to the overall increase in capacity versus the layers being sped up.
If an L2 hit is on the order of 200 cycles and it's 4MB, a cache 32x larger and outside of the L2 could add a significant amount of additive latency such that the average latency is worse than if it weren't there for pointer-chasing RT blocks.
For AMD, it's not an uncommon case that on-die traffic is as bad or worse than missing to DRAM.
Naughty Dog listed a worst-case scenario for the PS4 CPU being a remote hit to a Jaguar L1, and Zen 1 had noticeable inter-CCX latency on the order of missing to DRAM.
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