This looks like complete BS.
>MCM
Not likely from linux drivers pointing to a single unit. All signs show AMD will probably not make the move to multi die design this gen but at a later gen. From the XSX design, nothing seem to point to moving in this direction.
>3x L1 cache
Very unlikely since increasing a cache by 3x in size will generally kill latency most of the time. Also why would the L1 need to be 3x the size. From the XSX presentation it seem that L2 sizes per compute units are pretty much inline with Navi 10, no mention of L1 size. Would be a strange detail to leave out if this was a thing.
>2x ROPs
64 ROPs are assumed from Linux drivers. Which is the same as Navi10. AMD probably thinks 64ROPs are good enough for 4k. With higher clocks, they probably do have enough ROP performance with only 64. Although more could be a possibility and wouldn't be too surprising.
>7x performance in ML uses
From what? It's not like it has tensor cores. Could be int4 but thats very specific cases and would probably only be in inference. Also since RDNA is supposed to focus on gaming, it will be unlikely to really focus on ML performance improvements since CDNA is now a thing. Claiming 7x improvement as average of multiple use cases isn't likely at all even if the thing has a lot better performance.
>HBM
Not likely, also it shows 2 blocks? 2 stacks? which wouldn't be enough bandwidth.
Also why would anyone at AMD send anyone a picture like this? Both terrible as a technical document and looks terrible as marketing material too.