AMD: Navi Speculation, Rumours and Discussion [2019-2020]

To be the fair I believe the belief is that the PS5 has had so many revisions / respins on its silicon to reach that clock speed it didnt start like that.

 

Silly season is upon me.
I got a weird feeling AMD did a RV770 move again, everyone expecting a doubling of CUs to 80CUs, and they went a bit further.
I've always liked the 96CU(8x12,6x16) could potentially work well with HBM2 4096/3072bit or GDDR6 512bit/384bit.

 

Nah, the config is 80CUs scattered among 8SAs/4SEs.
It's in the driver code.

 

At what price...

 

Or maybe they’re sandbagging on RT and the “minimalist” approach was reserved for the consoles only with PC GPUs getting something better.

 

Wouldn't make much sense for either AMD or Sony/MS.

 

It could if they were constrained by power or transistor budget.

 

Posted on OCUK, sourced from Igor's Lab. Haven't located original post yet. Probably speculative

 

Locuza drew that lol

 

So just a mock up?

 

Yeah.

 

Well that's both disappointing and a relief at the same time

 

Unless this "super RT" method consumed a lot more power.


Though to be very clear, I don't believe in trinibwoy's speculation of AMD sandbagging on the consoles' RT. Cerny made mention of the PS5 using AMD's RT approach and Microsoft didn't make any claims on exclusive RT (like they did for e.g. VRS), so my guess is they're all using the "same" RT capabilities, at least considering general methodology and RT unit count per CU.


My speculation for RDNA2 is that it'll be:
- A lot more dense than RDNA1 regarding number of execution units per die area, even though it shares the same process (in this aspect it would indeed be similar to RV670 -> RV770);
- Clocking a lot higher than RDNA1, with desktop GPUs averaging at or above 2.2GHz.


If Big Navi is an 80 CU chip clocking at 2.2GHz and two 8GB stacks of HBM2E, then there's really no concern as to whether or not it can compete with GA102, in both absolute performance and power efficiency.

 

AMD itself said common RT platform between DT and console.

A bit.
Each WGP is actually smaller but ALU@mm^2 hasn't really gone up.

Yeah.
Built for speed.

It's not HBM and two 2.4Gbps stacks aren't enough anyway.

 

Now I'm really puzzled.

 

Big Navi supposedly uses GDDR6. 12, 24 or 48 GByte seem possible, if you accept the rumor of 384 bit bus.

 

GDDR6 it is.
Currently shipping HBM2E is 2.4Gbps so it's not a big win over G6@16Gbps even at three stacks.

Yeah I wanna some AIC vendor to do a 48gig N21 for kicks.
Why?
No idea, but might be fun.

 

Was kinda expecting them to go with 4 stacks of HBM2 for both bandwidth and power reasons.

 

They did, where it matters, see MI100.
Client gets simple G6 setup and a fancy new uArch focused on power and bandwidth efficiency and all that jazz.

 

They may do that for the Pro line/Apple MPX modules, like Navi 12.

So what’s the current speculation for VRAM bandwidth on Navi 21 with GDDR6?