3DLabs P20 Announced
- Thread starter Dave Baumann
- Start date
AAAAIIIEEEEEEEEE!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Tell us more, TELL US NOW!!!!!
(And sometimes Dave's teasing can make me snap....)
Tell us more, TELL US NOW!!!!!
(And sometimes Dave's teasing can make me snap....)
Thanks Zaphod!Zaphod said:
"The VSU is then able to drive two VPUs at full bandwidth over a 8.4GB/sec interface while optimally distributing graphical primitives between the two VPUs to achieve a genuine doubling of both geometry and fill-rate performance."
Cool. I was onlytalking about the possibility of doing this to Theo the other night. I didn't expect 3DLabs to actually be doing it.
Cool. I was onlytalking about the possibility of doing this to Theo the other night. I didn't expect 3DLabs to actually be doing it.
Joe DeFuria
Legend
God damn....SLI on steroids! 
Hmm...
1) I wonder how they count transistors. What I read indicates there is a separate VSU that can scale with multiple VPUs, and the VPU is listed as 150 million
.
2) When I see 3dlabs say "supporting advanced flow control" and review my impressions of P10, I tend to envision something more towards the expectations of R500 efficiency.
3) Support for floating point framebuffer, apparently. Possibly interesting for AA, depending on bandwidth and AA implementation efficiency. (Hmm...BTW, for whom does SA work, if it isn't a closely held secret)?
4) Floating point blending operations, it would seem...?
5) Mention of Hierarchical-Z, but not indication of Slipstream. 
Or is there?
6) 67 Gigaflops? Hmm...how are they counting that...the possibilities already out there are a bit staggering in terms of trying to guess where it stands performance wise, especially with my understanding of the multi-chip configurations. Wouldn't a 6800U pixel processing be at around 12 with the marketing slant of 2 ops per clock? Around 51 splitting up into components?
1) I wonder how they count transistors. What I read indicates there is a separate VSU that can scale with multiple VPUs, and the VPU is listed as 150 million
.2) When I see 3dlabs say "supporting advanced flow control" and review my impressions of P10, I tend to envision something more towards the expectations of R500 efficiency.
3) Support for floating point framebuffer, apparently. Possibly interesting for AA, depending on bandwidth and AA implementation efficiency. (Hmm...BTW, for whom does SA work, if it isn't a closely held secret)?
4) Floating point blending operations, it would seem...?
5) Mention of Hierarchical-Z, but not indication of Slipstream.
Or is there?6) 67 Gigaflops? Hmm...how are they counting that...the possibilities already out there are a bit staggering in terms of trying to guess where it stands performance wise, especially with my understanding of the multi-chip configurations. Wouldn't a 6800U pixel processing be at around 12 with the marketing slant of 2 ops per clock? Around 51 splitting up into components?
Joe DeFuria
Legend
Seiko said:
It looks to me like it might be the following:
* 2 VPUs on one board, in the PCI-E x16 slot.
* The VSU on a second PCI-E (x1? x16?) slot, feeding the primitives to the dual chip card.
demalion said:
It talks of SuperScene AA, and if this has similarities to the old SuperScene AA we looked at before, it would appear to have stocastic sampling and separate buffers for the pixels that do or don't require subsamples.
I know the Hier-Z is implemented similar to ATI's. Slipstream 1 was mainly software and I doubt they would want it for a predomanently high end product, workstation product.
jolle said:
3Dlabs have been delivering full virtualised RAM since Wildcat and virtualised texturing for many, many years.
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