"2x the power of the GC," can someone clarify what this means? (ERP)
- Thread starter Li Mu Bai
- Start date
I'm thinking of GC's in general (and DC's in general too). It's probably not that the console is producing a lot of noise, just something about the note the fan makes. Larger slower fans would be my choice (decent bearing ones) though size is obviously limited by the console's design.
Thunder Emperor
Newcomer
Just to throw some fuel out there, we know the lindbergh board for Sega acardes runs on a geforce 6 card http://i3.photobucket.com/albums/y53/gokou20/g6.jpgwhich is less than the RSX of Xenon,
but we know it can push this
So since the Revs graphical capabiliteis is equal to an x800 whichis on par or slighlty better than a Gefroce 6 then. We can expect these kinds of graphics.
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but we know it can push this
So since the Revs graphical capabiliteis is equal to an x800 whichis on par or slighlty better than a Gefroce 6 then. We can expect these kinds of graphics.
[Moderator : We have rules about image size, please follow them.]
Megadrive1988
Veteran
huh ? there's no confirmation that the ATI Hollywood GPU in Revolution is equivalent in power to an R420 ~ Radeon X800, therefore making Revolution equal to or greater than Lindbergh GPU.
Thunder Emperor
Newcomer
Megadrive1988 said:
I was refering to a qutoe from Feb edge magazine, where it was stated the graphical prowless of the rev ws equal to a dual core cpu and an ati x800 Gpu.
this i sthe quote.
“How much better, goes Nintendo’s reckoning, does Mario, a cartoon-styled character with a simple, bold-hued outfit, need to look? It’s a fair point. How much better does the next Metroid Prime need to look? The answer is said to be about on par with what a dual-core-CPU PC running an X800 graphics card could manage.â€
That is why i made the comparison
But don't forget that the arcade board has ample of space for cooling. The geforce cooler alone is almost as high as the entire Revolution. Plus revolution is likely to have less memory than the Lindbergh, etc. It's just not a very viable comparison.
BTW, your pic exceeds the size limit, as stated in the forum rules.
BTW, your pic exceeds the size limit, as stated in the forum rules.
pc999 said:
In the beginning the GC was indeed sold at a loss, but became profitable for almost the following 2 years iirc. Primarily all of '02 & the majority of '03 at the $149.99 price-point. After steadily declining market share & retailer demand even halting GC production for a time, Nintendo lowered the price to $99 in October of '03. Even then the platform was only losing $10-15 dollars per console. To further cut any continuing losses however in May of '04 Nintendo opted to remove the digital A/V output
(the DOL-101 revision) & move primary GC manufacturing to China. This allowed Nintendo to sell their consoles now at cost, or for a negligible profit.
Yes Quad-core is the same as 1T-SRAM-Q. It's name is derived from the fact that it is 4x as dense as conventional 6T-SRAM memory solutions, & its bit cell is 2x as small as those of 1T-SRAM's. (with major enhancements over both) I've written about it in the past here, & my next post will provide all the information you could want to know about the Rev's main & embedded memory pools.
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Thunder Emperor
Newcomer
hupfinsgack said:
sorry about the pic size. forgot to crop it.
Everything you could've wanted to know about 1T-SRAM-Q
Why memory density & the unique aspects of MoSys Quad-core ram are integral in the Revolution's design objectives become readily apparent once we delve into its capabilities & fabrication. This is actually the fourth generation produced by MoSyS & is by far the most impressive. Technical advancements of the previous 3 iterations are all incorporated within the Revolution's 1T-SRAM-Q. (1T-SRAM, 1T-SRAM-M, & 1T-SRAM-R) Nintendo is aiming roughly for around these outside case dimensions. 1.9"(H) x 6.5"(W) x 8.5"(D)=105 inches cubed As an aside memory was occupying over 50% SOC (system on chip) silicon area at the end of 2002, 71% in '05, & an estimated 90% in 2014 if not sooner. (obviously not necessarily in reference to console platforms, but the RAM technology sector in general) 2002 was also the 1st time memory content surpassed even logic content on chip.
One of the reasons why 1T-SRAM-Quad-core is so important to such a small casing design like the Rev's. is that its density allows for a substantially smaller memory bit cell while retaining the same bit capicatance as 1T-SRAM, while reducing its size x2 as I stated previously. (further reducing the necessary on die space) MoSys introduced its first-generation 1T-SRAM that delivered twice the density of 6T-SRAM while using standard CMOS logic processes (complementary metal-oxide-semiconductor) that the GC incorporated. 1T-SRAM-Q, like 1T-SRAM retains the refresh free, single-cycle operations for greater data throughput like its referenced namesake. (6T-SRAM) Acheived by MoSys's patented Multi-Bank architecture. Which essentially partitions its memory into small banks, during each banks normal idle cycles internal refresh management circuitry ensures that each cell’s capacitor retains its charge by performing refresh operations that occur transparently in the background, independent of the system interface simultaneously without ever affecting either the read or write cycles. Even banks that are accessed for prolonged periods can nevertheless refresh thanks to a unique caching scheme that ensures periodic idle cycles even for those active banks.
What 1T-SRAM-Q took from the second generation M is its dramatically lower standby power characteristics. 1T-SRAM-M features unique leakage suppression circuitry that achieves standby current as low as 10μA/Mbit with full data retention. Initially intended for mobile applications, & optional for those designers who want to include these power conserving & leakage controlling functions in Q-core, which I'm sure Genyo Takeda (Nintendo's lead console development engineer) & his core of engineers in all probability did. You can begin to see why this ram solution would have looked more & more attractive to Nintendo's low-power consumption philosophy, in addition to the Rev's smaller form function. With the 3rd generation R, MoSys refined & enhanced the quality & reliability of embedded ram as designers began adding more blocks comprising larger memory arrays to SoCs. Embedded ram, & specifically its quality had emerged as an issue of concern.
In addition R improved yields during manufacturing, improved reliability after manufacturing and enhanced soft error rate (SER) during product use. With 1T-SRAM-R, MoSys augmented the basic 1T-SRAM architecture with an enhanced reliability option called Transparent Error Correction (TEC™) – a MoSys patented technology that eliminates the need for costly repair during manufacture or slow self-repair at power-up. Unlike conventional redundancy-based repair approaches, TEC dynamically repairs errors during manufacturing, avoiding the additional manufacturing costs and delays associated with laser repair during production. Furthermore, TEC dynamically repairs errors during use, providing SER under 10 FITs/Mbit – 1,000x less than that of 6T SRAM. While conventional ECC approaches add 20 to 30% more area for additional redundant memory bits, TEC adds essentially no additional area. Although it uses 20% more bit cells, its bit cells are 20% smaller than even 1T-SRAM's cells. They enhanced the comprehensive quality of embedded ram without the requisite silicon overhead, since MoSys utilizes metal instead of silicon.
Now finally onto the 4th generation, 1T-SRAM-Q. It posseses all of the aforementioned features plus an innovative trademarked capacitor, dubbed the Folded Area Capacitor (FAC) technology. 1T-SRAM-Q memory provides a very high-density embedded memory solution, requiring only an additional non-critical mask and two simple steps that exert no adverse affects on logic. With this technology, SoC designers can begin to achieve true system-level memory solutions, incorporating arrays of over 128 Mb at 0.13 μm and over 256 Mb at 90nm. (if only, but there would be no possible way Nintendo could include 256mb or more of Quad-core while still offering the system at its projected price point of $200-250) At these memory sizes, designers can integrate main memory on SoCs, reducing external chip count while speeding overall application performance.
In memory technology, smaller means faster timing and lower power operation, because operating characteristics can scale down with the smaller bit cell. A smaller cell means shorter metal bit lines, which translates to reduced parasitics. In turn, reduced parasitics enable faster timing and higher performance. Besides shorter metal bit lines, 1T-SRAM-Q memory’s shorter metal word lines mean faster charging and discharging – and faster read and write cycles. In fact, while 1T-SRAM's technology has provided 40%-50% speed improvements at each succeeding technology node, these factors enable 1T-SRAM-Q memory to offer a 10 to 20 percent speed improvement over 1T-SRAM memory at the same process node. (which of course we know will not be the case here, 90nm Quad-core for the Revolution)
In fact, 1T-SRAM-Q technology offers another fundamental advantage in signal integrity, which can also lead to further memory enhancements. The 1T-SRAM-Q capacitor provides about the same charge storage as the 1T-SRAM capacitor. Because its bit cell is 2x smaller than the 1T-SRAM cell, however, 1T-SRAM-Q technology provides an improved ratio of stored charge to parasitics, resulting in an improved signal-to-noise ratio (SNR). Typically, high-density designs face tighter signal margins as voltages drop in more advanced process technologies at 90nm and below. With its improved SNR, however, 1T-SRAM-Q can take advantage of additional available timing margin to speed performance or increase reliability for applications that do not require clock rates at the edge of the envelope.
The favorable ratio of charge to bit cell circuitry also translates directly into reduced power-dissipation characteristics for 1T-SRAM-Q memory solutions. Shorter wires, fewer parasitics and lower voltage combine to reduce 1T-SRAM-Q memory’s dynamic power requirements without ever negatively impacting its speed or reliability.
Using an additional mask, (one of the two steps I mentioned prior) the 1T-SRAM-Q's fabrication process uses two extra steps to etch a well in the shallow trench isolation (STI) layer and fill it with polysilicon. Oxide forms naturally, bending from the horizontal plate down into the well creating the 1T-SRAM-Q’s Folded Area Capacitor. The FAC well reaches deep into the STI layer, providing a robust capacitor structure that retains a large effective area – and charge – even as the bit cell is scaled down to more advanced technology nodes at 65nm and 45nm.
.
The additional etch and implant steps occur before the transistors are even fabricated, so this approach introduces no extra thermal cycles. In contrast, embedded DRAM requires process changes that cause additional thermal cycles. These additional heating and cooling passages affect the characteristics of the logic transistors. As a result, embedded DRAM processes are inevitably different from standard logic processes, and logic transistors produced with embedded DRAM processes do not have quite the same performance as those produced with standard logic processes. Because 1T-SRAM-Q memory’s process does not introduce additional thermal cycles, engineers can be confident that this process does not impact the performance of the rest of the chip. Furthermore, the 1T-SRAM-Q's process does not result in any adverse topography, because there are no FAC structures rising higher than the plane to affect layers placed above it.
So as you can see, (or I have hopefully demonstrated) why 1T-SRAM-Q was the perfect memory solution for the Revolution even over XDR & GDDR3 as well. A comparative analysis of all 3's features including speed will be forthcoming in my next post.
Why memory density & the unique aspects of MoSys Quad-core ram are integral in the Revolution's design objectives become readily apparent once we delve into its capabilities & fabrication. This is actually the fourth generation produced by MoSyS & is by far the most impressive. Technical advancements of the previous 3 iterations are all incorporated within the Revolution's 1T-SRAM-Q. (1T-SRAM, 1T-SRAM-M, & 1T-SRAM-R) Nintendo is aiming roughly for around these outside case dimensions. 1.9"(H) x 6.5"(W) x 8.5"(D)=105 inches cubed As an aside memory was occupying over 50% SOC (system on chip) silicon area at the end of 2002, 71% in '05, & an estimated 90% in 2014 if not sooner. (obviously not necessarily in reference to console platforms, but the RAM technology sector in general) 2002 was also the 1st time memory content surpassed even logic content on chip.
One of the reasons why 1T-SRAM-Quad-core is so important to such a small casing design like the Rev's. is that its density allows for a substantially smaller memory bit cell while retaining the same bit capicatance as 1T-SRAM, while reducing its size x2 as I stated previously. (further reducing the necessary on die space) MoSys introduced its first-generation 1T-SRAM that delivered twice the density of 6T-SRAM while using standard CMOS logic processes (complementary metal-oxide-semiconductor) that the GC incorporated. 1T-SRAM-Q, like 1T-SRAM retains the refresh free, single-cycle operations for greater data throughput like its referenced namesake. (6T-SRAM) Acheived by MoSys's patented Multi-Bank architecture. Which essentially partitions its memory into small banks, during each banks normal idle cycles internal refresh management circuitry ensures that each cell’s capacitor retains its charge by performing refresh operations that occur transparently in the background, independent of the system interface simultaneously without ever affecting either the read or write cycles. Even banks that are accessed for prolonged periods can nevertheless refresh thanks to a unique caching scheme that ensures periodic idle cycles even for those active banks.
What 1T-SRAM-Q took from the second generation M is its dramatically lower standby power characteristics. 1T-SRAM-M features unique leakage suppression circuitry that achieves standby current as low as 10μA/Mbit with full data retention. Initially intended for mobile applications, & optional for those designers who want to include these power conserving & leakage controlling functions in Q-core, which I'm sure Genyo Takeda (Nintendo's lead console development engineer) & his core of engineers in all probability did. You can begin to see why this ram solution would have looked more & more attractive to Nintendo's low-power consumption philosophy, in addition to the Rev's smaller form function. With the 3rd generation R, MoSys refined & enhanced the quality & reliability of embedded ram as designers began adding more blocks comprising larger memory arrays to SoCs. Embedded ram, & specifically its quality had emerged as an issue of concern.
In addition R improved yields during manufacturing, improved reliability after manufacturing and enhanced soft error rate (SER) during product use. With 1T-SRAM-R, MoSys augmented the basic 1T-SRAM architecture with an enhanced reliability option called Transparent Error Correction (TEC™) – a MoSys patented technology that eliminates the need for costly repair during manufacture or slow self-repair at power-up. Unlike conventional redundancy-based repair approaches, TEC dynamically repairs errors during manufacturing, avoiding the additional manufacturing costs and delays associated with laser repair during production. Furthermore, TEC dynamically repairs errors during use, providing SER under 10 FITs/Mbit – 1,000x less than that of 6T SRAM. While conventional ECC approaches add 20 to 30% more area for additional redundant memory bits, TEC adds essentially no additional area. Although it uses 20% more bit cells, its bit cells are 20% smaller than even 1T-SRAM's cells. They enhanced the comprehensive quality of embedded ram without the requisite silicon overhead, since MoSys utilizes metal instead of silicon.
Now finally onto the 4th generation, 1T-SRAM-Q. It posseses all of the aforementioned features plus an innovative trademarked capacitor, dubbed the Folded Area Capacitor (FAC) technology. 1T-SRAM-Q memory provides a very high-density embedded memory solution, requiring only an additional non-critical mask and two simple steps that exert no adverse affects on logic. With this technology, SoC designers can begin to achieve true system-level memory solutions, incorporating arrays of over 128 Mb at 0.13 μm and over 256 Mb at 90nm. (if only, but there would be no possible way Nintendo could include 256mb or more of Quad-core while still offering the system at its projected price point of $200-250) At these memory sizes, designers can integrate main memory on SoCs, reducing external chip count while speeding overall application performance.
In memory technology, smaller means faster timing and lower power operation, because operating characteristics can scale down with the smaller bit cell. A smaller cell means shorter metal bit lines, which translates to reduced parasitics. In turn, reduced parasitics enable faster timing and higher performance. Besides shorter metal bit lines, 1T-SRAM-Q memory’s shorter metal word lines mean faster charging and discharging – and faster read and write cycles. In fact, while 1T-SRAM's technology has provided 40%-50% speed improvements at each succeeding technology node, these factors enable 1T-SRAM-Q memory to offer a 10 to 20 percent speed improvement over 1T-SRAM memory at the same process node. (which of course we know will not be the case here, 90nm Quad-core for the Revolution)
In fact, 1T-SRAM-Q technology offers another fundamental advantage in signal integrity, which can also lead to further memory enhancements. The 1T-SRAM-Q capacitor provides about the same charge storage as the 1T-SRAM capacitor. Because its bit cell is 2x smaller than the 1T-SRAM cell, however, 1T-SRAM-Q technology provides an improved ratio of stored charge to parasitics, resulting in an improved signal-to-noise ratio (SNR). Typically, high-density designs face tighter signal margins as voltages drop in more advanced process technologies at 90nm and below. With its improved SNR, however, 1T-SRAM-Q can take advantage of additional available timing margin to speed performance or increase reliability for applications that do not require clock rates at the edge of the envelope.
The favorable ratio of charge to bit cell circuitry also translates directly into reduced power-dissipation characteristics for 1T-SRAM-Q memory solutions. Shorter wires, fewer parasitics and lower voltage combine to reduce 1T-SRAM-Q memory’s dynamic power requirements without ever negatively impacting its speed or reliability.
Using an additional mask, (one of the two steps I mentioned prior) the 1T-SRAM-Q's fabrication process uses two extra steps to etch a well in the shallow trench isolation (STI) layer and fill it with polysilicon. Oxide forms naturally, bending from the horizontal plate down into the well creating the 1T-SRAM-Q’s Folded Area Capacitor. The FAC well reaches deep into the STI layer, providing a robust capacitor structure that retains a large effective area – and charge – even as the bit cell is scaled down to more advanced technology nodes at 65nm and 45nm.
.
The additional etch and implant steps occur before the transistors are even fabricated, so this approach introduces no extra thermal cycles. In contrast, embedded DRAM requires process changes that cause additional thermal cycles. These additional heating and cooling passages affect the characteristics of the logic transistors. As a result, embedded DRAM processes are inevitably different from standard logic processes, and logic transistors produced with embedded DRAM processes do not have quite the same performance as those produced with standard logic processes. Because 1T-SRAM-Q memory’s process does not introduce additional thermal cycles, engineers can be confident that this process does not impact the performance of the rest of the chip. Furthermore, the 1T-SRAM-Q's process does not result in any adverse topography, because there are no FAC structures rising higher than the plane to affect layers placed above it.
So as you can see, (or I have hopefully demonstrated) why 1T-SRAM-Q was the perfect memory solution for the Revolution even over XDR & GDDR3 as well. A comparative analysis of all 3's features including speed will be forthcoming in my next post.
Last edited by a moderator:
darkblu said:
Why?, 64MB of 2GB/s DRAM would cost almost nothing to include in the console.
hupfinsgack said:
A-Ram just means Auxiliary Ram), its not actually a kind of ram.
hupfinsgack said:
If its as powerful its as powerful, the cooling solution it uses is irrelivant. Or are you saying that you don't believe that Revolutions GPU will be as powerful as a X800?
Ooh-videogames
Regular
Great post Li, can't wait for the next one. The low power consumption is great for embedded designs. I've always wonder about the speed comparisons between 1T-SRAM-Q and XDR/GDDR3. Nowing these characteristics, could someone come up with an estimate of how much silicon or die sze we could expect from Hollywood considering it should have embedded memory?
Teasy said:
Plus there is two things to consider 1) diferent process 2) probably diferent architetures becuse they didnt said it would be X800 GPU just that it will be as powerfull and based on some key parts of the R300 (just to give a eg) under that description a X1600 would fit perfectly (althought using is strenghts with others focus) and that is already used on laptops, so I dont think that it case size would be a problem.
Ooh-videogames
Regular
pc999 said:
I think we should expect more, Hollywood probably has tapped out. If developers can expect to have final hardware by June. This would mean that whatever the design is its more closer to a X1600 IMO.
I know, I was refering to the bandwith of 81MB/s.Teasy said:
I am rather implying that we won't be seing anything resembling an off-shelf component. So the comparison is flawed from the beginning.
Ooh-videogames said:
From an IGN interview
This sounds like Hollywood has indeed tapped out.
Ooh-videogames
Regular
I wonder which GPU had tapped out first, Hollywood or RSX?
This has always been a question of mine concerning Revolution, with many next gen engines being created, does the Revolution have what it takes to run them?
Trying to think technically here so bare with me, please. If we are to assume that the Revolution will be capable of doing everyone of those features presented in the Crysis footage, then Hollywood should have PS 3.0. So I'm led to the question of what pixel shader pipeline numbers would be needed, also TMU's?
I'm not expecting the console to match 360/PS3 when it comes to how much can be displayed on screen at once.
Do developers need the exact same number of pixel pipelines in Xenos/RSX, just to have features like Volumetric Clouds, Soft Shadows, Realtime Ambient Lighting be technically possible on Revolution?
This has always been a question of mine concerning Revolution, with many next gen engines being created, does the Revolution have what it takes to run them?
Trying to think technically here so bare with me, please. If we are to assume that the Revolution will be capable of doing everyone of those features presented in the Crysis footage, then Hollywood should have PS 3.0. So I'm led to the question of what pixel shader pipeline numbers would be needed, also TMU's?
I'm not expecting the console to match 360/PS3 when it comes to how much can be displayed on screen at once.
Do developers need the exact same number of pixel pipelines in Xenos/RSX, just to have features like Volumetric Clouds, Soft Shadows, Realtime Ambient Lighting be technically possible on Revolution?
Well since we don't really have any feature list neither performance data regarding the Revolution it's pretty hard to tell whether next gen engine will run on it or not.
Assuming it's R3xx level or better, then yes, next gen engine will run, provided the CPU follows...
Basically the Revolution would (according to our hints and assumptions) play the same games as competitors but at lower resolution.
Assuming it's R3xx level or better, then yes, next gen engine will run, provided the CPU follows...
Basically the Revolution would (according to our hints and assumptions) play the same games as competitors but at lower resolution.
Ooh-videogames said:
You can try think in other way, if games like Crysis, UT07, MoH:A and a few next gen games/engine that will appear on the PC till the end of this year or mid 07, those will NEED to run well and fully featured in mid end cards from today (just like mid end cards from the H2 of 2004 like the 6600/X700run todays games) but only at lower rez, for the CPU they will need to run well on a sigle core too, so if we assume (and we do had a lot of hint to that) that it will be as powerfull as a X800/X1600 or something like and a dual core PC CPU , then it should be very good to games like those (althought memory may be a limit).
Now what you really need is decide in what do you want to belife.
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