AMD Execution Thread [2024]

I'm curious
Well, making 2CCD SKUs with 3D cache on both this time has been mentioned already.
Another obvious option is to move away from 8C CCDs to 12C or even 16C ones - which should be possible on current production lines.
Upgrading the IOD from the one used in Zen 4 could also bring sizeable benefits in RAM speeds/latencies.
That's off the top of my head.
 
I thought 16C-32C comes with 2nm. You can't just increase the core count without increasing L3 to compensate the bandwidth requirements. Anybody here knows if these L3 have a scheduler to handle parallel reads if possible(reads, different lines, no write conflicts) for CCDs? At what point does this become a bottleneck?
 
Chips and cheese has a new article talking about 9800X3D's new 3D V Cache:


From my understanding, the 3D V Cache is just a capacity expansion over the existing L3 cache, there's no extra port (otherwise it can and should be called a L4 cache).
 
Chips and cheese has a new article talking about 9800X3D's new 3D V Cache:


From my understanding, the 3D V Cache is just a capacity expansion over the existing L3 cache, there's no extra port (otherwise it can and should be called a L4 cache).
Yes, it's just a capacity expansion, exact same cache level.
 
I thought 16C-32C comes with 2nm. You can't just increase the core count without increasing L3 to compensate the bandwidth requirements. Anybody here knows if these L3 have a scheduler to handle parallel reads if possible(reads, different lines, no write conflicts) for CCDs? At what point does this become a bottleneck?

Technically 5nm 16C CCDs were already a thing with Zen 4C in Bergamo, though it was a 2 CCX design. And 1 CCX 16C Zen5c CCDs on 3nm are available on Turin dense.

Rumour is 32C Zen6C on 2nm, and that there will also be 8 and 16 core CCDs well, though the rumour didn't specify which type of core. I suspect it might be Zen 6 standard, to enable Venice with 192C (16C x 12 CCDs), and Venice dense with 256 cores (32C X 8 CCDs).
 
AMD is letting go of 4% of it's global workforce to "align AMD resources with our largest growth opportunities".

In a statement given to Wccftech, an AMD spokesperson confirmed the layoffs. According to AMD, the layoffs are "a part of aligning our resources with our largest growth opportunities." They are part of "a number of targeted steps that will unfortunately result in reducing our global workforce by approximately 4%." AMD added that it is "committed to treating impacted employees with respect and helping them through this transition."

 

The author seems to have made up this statement completely out of thin air. There are some rumours of an AMD ARM APU called Sound Wave (Though I would doubt even that tbh), but there's absolutely nothing to suggest AMD is working on an ARM server chip, nor would AMD have any incentive to compete with its own x86 chips. The article is clear that AMD is only supplying Instinct GPUs and software support.
 
A new rumor about future AMD GPUs:

-There is no RDNA5 code name. After RDNA4, it will be UDNA.
-MI400 and RX9000 use the same UDNA, and the architecture uses an ALU design similar to GCN.
-UDNA Gaming GPU is tentatively scheduled for mass production in Q2 26.
-Sony's PS6 will use UDNA, and the CPU has not yet been determined to be ZEN4 or ZEN5.

 
A new rumor about future AMD GPUs:

-There is no RDNA5 code name. After RDNA4, it will be UDNA.
-MI400 and RX9000 use the same UDNA, and the architecture uses an ALU design similar to GCN.
-UDNA Gaming GPU is tentatively scheduled for mass production in Q2 26.
-Sony's PS6 will use UDNA, and the CPU has not yet been determined to be ZEN4 or ZEN5.

GCNbros… we are so back.

It’s so interesting to watch this develop. RDNA was supposed to be the great comeback for Radeon, as gaming cards could be untethered from DC designs. However I guess that makes little sense as very few bought into RDNA.
 
-Sony's PS6 will use UDNA, and the CPU has not yet been determined to be ZEN4 or ZEN5.
If Sony is going for UDNA why would they use by all means ancient CPUs to accompany it? There will be at least Zen 6 ready in similar timeframe, if not Zen 7.
 
If Sony is going for UDNA why would they use by all means ancient CPUs to accompany it? There will be at least Zen 6 ready in similar timeframe, if not Zen 7.
Console APUs tend to be extremely die size (manufacturing cost) constrained, and I wouldn't be shocked if they were targeting a node or 3 down from the bleeding edge, along with the CPU designs to match. Newer cores in general tend to require more transistors every generation. I could see them going Zen4c or Zen5c for that time frame and whatever the most budget friendly 3nm-class node there is on offer.
 
GCNbros… we are so back.

It’s so interesting to watch this develop. RDNA was supposed to be the great comeback for Radeon, as gaming cards could be untethered from DC designs. However I guess that makes little sense as very few bought into RDNA.

Hmmmm it’ll definitely be interesting to see how this unified arch plays in games. With RT and upscaling becoming more prevalent shaders are likely to get even more branchy.

Will UDNA stick with 64-wide wavefronts executed over 4 clocks?
 
This looks to be MI300C, which was rumoured to be cancelled. I think they are going for only GPU/AI based chiplets for the next gen MI series though, no more CPU hybrids.

Console APUs tend to be extremely die size (manufacturing cost) constrained, and I wouldn't be shocked if they were targeting a node or 3 down from the bleeding edge, along with the CPU designs to match. Newer cores in general tend to require more transistors every generation. I could see them going Zen4c or Zen5c for that time frame and whatever the most budget friendly 3nm-class node there is on offer.

Yep, people forget that the PS5 and Xbox Series X/S in late 2020 used a Zen 2 mobile implementation (essentially a "c" version with half the L3) even though Zen 3 was out by that time. And the SoCs were on 7nm even though Apple was shipping 5nm by then. Zen 5c wouldn't be a surprise considering the die size is very similar to Zen 4 as Zen 6 would presumably increase the die size a fair bit. The GPU IP is likely to be newer as it is larger and needs to be more area efficient IP. Agreed on the node as well, N2 or newer would be too expensive for anything except AI/HPC or flagship SoCs. I would expect the next gen console chips to be on a density optimized 3nm node, possibly N3S.
 
In general I'm not to sure how relevant "bleeding edge" CPU performance is for a console. We kind of want them on the PC for gaming because we're trying to basically brute force games optimized to 60 (or 30) fps to higher frame rates.

A PS6 would likely be designed more so with VRR in mind and have other techniques to aim for 60 fps and higher in terms of playable stability. Another 20% faster CPU or whatever is not likely to be the limitation.

If cross gen is also going to be the focus then you can't really design the core gameplay around a much faster CPU either as that wouldn't scale backwards to the PS5/pro.

Also as mentioned somewhat above it's worth keeping in mind Zen 2 APUs on the consoles are actually rather slow/behind. Zen 4 (or 5) by itself is a rather significant 50%+ increase already depending on the implementation context. The general direction also is likely to move more off to the GPU or even other dedicated units (eg. decompression this gen).
 
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