AMD Execution Thread [2024]

[fehu]

This being said AMD certainly has a couple of aces up their sleeves which they may want to use in AM5

I'm curious

 

[DegustatoR]

I'm curious

Well, making 2CCD SKUs with 3D cache on both this time has been mentioned already.
Another obvious option is to move away from 8C CCDs to 12C or even 16C ones - which should be possible on current production lines.
Upgrading the IOD from the one used in Zen 4 could also bring sizeable benefits in RAM speeds/latencies.
That's off the top of my head.

 

[Nisaaru]

I thought 16C-32C comes with 2nm. You can't just increase the core count without increasing L3 to compensate the bandwidth requirements. Anybody here knows if these L3 have a scheduler to handle parallel reads if possible(reads, different lines, no write conflicts) for CCDs? At what point does this become a bottleneck?

 

[pcchen]

Chips and cheese has a new article talking about 9800X3D's new 3D V Cache:

AMD's 9800X3D: 2nd Generation V-Cache

Following the first generation of V-Cache found in the Zen 3 and Zen 4 X3D SKUs, AMD is now following up with the second generation of V-Cache which is a major change for AMD in terms of packaging.

chipsandcheese.com

From my understanding, the 3D V Cache is just a capacity expansion over the existing L3 cache, there's no extra port (otherwise it can and should be called a L4 cache).

 

[Kaotik]

Chips and cheese has a new article talking about 9800X3D's new 3D V Cache:

AMD's 9800X3D: 2nd Generation V-Cache

Following the first generation of V-Cache found in the Zen 3 and Zen 4 X3D SKUs, AMD is now following up with the second generation of V-Cache which is a major change for AMD in terms of packaging.

chipsandcheese.com

From my understanding, the 3D V Cache is just a capacity expansion over the existing L3 cache, there's no extra port (otherwise it can and should be called a L4 cache).

Yes, it's just a capacity expansion, exact same cache level.

 

[Erinyes]

I thought 16C-32C comes with 2nm. You can't just increase the core count without increasing L3 to compensate the bandwidth requirements. Anybody here knows if these L3 have a scheduler to handle parallel reads if possible(reads, different lines, no write conflicts) for CCDs? At what point does this become a bottleneck?

Technically 5nm 16C CCDs were already a thing with Zen 4C in Bergamo, though it was a 2 CCX design. And 1 CCX 16C Zen5c CCDs on 3nm are available on Turin dense.

Rumour is 32C Zen6C on 2nm, and that there will also be 8 and 16 core CCDs well, though the rumour didn't specify which type of core. I suspect it might be Zen 6 standard, to enable Venice with 192C (16C x 12 CCDs), and Venice dense with 256 cores (32C X 8 CCDs).