NCU: (/phy)
Next-Generation Compute Units having configurable double precision rate with
512 8-bit ops per clock, 256 16-bit ops per clock, or 128 32-bit ops per clock.
HBCC:
High Bandwidth Cache Controller: Able to cache assets on card memory, system memory, system NVRAM(disk), and network-attached memory/storage. Able to intelligently split assets between the above, to store partial assets in each area, and access them without introducing lag. This is further enhanced by a shared L2 cache between geometry, compute and pixel engines, as well as a direct connection from each engine to the HBCC's large data store.
DSBR:
Draw-Stream Binning Rasterizer culls pixels that are not visible in the final scene due to being obscured by other objects closer to the player "camera."
NGG: Next-Generation Geometry Path is the combination of the PS and IWD.
PS:
Primitive Shader discards obscured geometry before it is rendered.
IWD:
Intelligent Workgroup Distributor IWD programs each shader automatically with geometry, pixel, and compute instructions. It also minimizes context switching, by keeping assets that will be re-used in cache for longer.
