102 both ways where?
Xbone has no double-ported RAM, you can't both read and write simultaneously to either SRAM array or main DRAM.
AMD: Pirate Islands (R* 3** series) Speculation/Rumor Thread
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Xbone has no double-ported RAM, you can't both read and write simultaneously to either SRAM array or main DRAM.
It's 204 GB/s, 109 GB/s when running pure reads or pure writes, and 204 GB/s peak if using the interface in both directions to its maximum capacity. In the fully-loaded scenario, there is a bubble on the write path every 8 cycles.
This has been covered in the console threads since this is a console-specific issue.
With banking, it is possible to run multiple accesses from storage, even if the individual storage arrays cannot handle more than one access at a time.
This has been covered in the console threads since this is a console-specific issue.
With banking, it is possible to run multiple accesses from storage, even if the individual storage arrays cannot handle more than one access at a time.
Now seems quite an exciting time for Richard Huddy and his skill-set to be back at AMD, what with Mantle, upcoming DirectX 12, and the console design wins.
http://forums.anandtech.com/showpost.php?p=36527451&postcount=78
If the 500mm2+ GPU is Fiji we have interesting times coming around Q4 this year.
If the 500mm2+ GPU is Fiji we have interesting times coming around Q4 this year.
Sounds more likely the tiles of IP to me.
28HPM?
http://www.chipworks.com/en/technic...og/a-review-of-tsmc-28-nm-process-technology/
One could see that working for GPUs too?
Xbox One SOC is an HPM chip, so yes.
Yes, but the Xbox One isn't the kind of chip that you push to extremes. If the unknown chip in question is a big die GPU running at the usual high clock speeds, and this is indeed HPM, then what's the point of having a super fast process?
It's not that it's just a super fast process, it also has better power numbers especially leakage. For a very large die, leakage will be a significant factor and since we're already pushing hunderds of watts for the GPU, anything that increases performs per watt is good.
I know HPM is better wrt leakage. But that doesn't help you if it has a higher Vcc (does it?) which results in higher dynamic power. And AFAIK its speed is slower too: it's not a super fast process compared to the fastest no hold barred process. And there's no point in making a super large die with a slower process.
Edit: according to the TSMC table, HPM has similar speeds as HP, but Vcc is 0.9 vs 0.85V.
Maybe that's sufficient...
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Hawaii is 4XXmm² (I forget how much exactly) and already very close to the 300W limit at 1GHz. So perhaps this even bigger chip is meant to be run at somewhat lower clock speeds, at which point HPM makes sense.
Or maybe the processes have evolved since they were introduced and HPM is now a better option at 1GHz than it used to be.
There might be architectural changes lowering power consumption, too.
itsmydamnation
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if finfets offer there best performance/power @ ~0.7 volts and your already power constrained it does make sense to start the process of targeting that over 2-3 generations (backend of 28 , 20 and then finally finfet 16).
Interesting recent AMD research paper on TOP-PIM: Throughput-Oriented Programmable Processing in Memory.
Seems to include the 25x improvement of system performance comment that was made recently.
Things get interesting on page 8 and onward.
Adding compute units to the logic die found at the bottom of the memory stack.
Seems to include the 25x improvement of system performance comment that was made recently.
Things get interesting on page 8 and onward.
Adding compute units to the logic die found at the bottom of the memory stack.