By "high-level changes" I mean "improvements that change enough stuff to be obvious on the simplistic block diagrams that IHVs are willing to disclose". By this definition, all recent NV architectures featured high-level changes.
GCN has already seen big front-end changes. What will happen over the next year is an open question.
Changes in SM is much easier then changes in geometry flow because you can keep interfaces similar or even same. GT200 was smaller change but took longer then planned because it was not high priority project initially. Fermi was as big a change as G80. Very complex. Maybe a bit too much in one go. Kepler was easier.
I would expect the current interconnect and GPCs to remain for at least a couple of generations past Kepler; I've been also told that it's not likely that we'll see changes for SIMD32 configs in their ALUs any time soon. Apart from that there aren't going to be any huge fireworks IMHO and as long as efficiency rises as expected with every new generation I don't think many will complain. What they could change is to decouple ROPs from the MC, but I don't think that it belongs to something people would consider as "important".
GT200 was supposed to fill the ~18 month gap to the Fermi launch in late '09 that, as we all know, didn't happen. The strategy was similar to the DX9-DX10 transition, where G70 played the same role as GT200 -- both architectures were simply more of the same from the preceding generation, not a major invention. A straightforward performance upgrade with few small arch tweaks.
Now, the situation with Fermi is a bit different, me thinks. Kepler is definitely a bit more than a performance scale up.
Now, the situation with Fermi is a bit different, me thinks. Kepler is definitely a bit more than a performance scale up.
Last edited by a moderator:
There's some stuff I would expect to see on Maxwell (the hierarchical scheduling and register file stuff that Dally and others wrote a paper on) that I would count as a pretty major change. I also remember seeing a presentation by Dally where he said that he's been trying to push for a different kind of network-on-chip at NVidia, so maybe something will happen there? Though, Ailuros says no and seems to have inside info.
Changes to the interconnect, which I understand to mean the network(s) by which different elements on the chip communicate. This sounds like it's a cross-bar in current NVidia chips, but as far as I know, there are topologies (e.g. flattened butterfly) that have better energy delay products.
Out of curiousity is there an estimate how much they could gain in terms of power with something like a flattened butterfly?
Any relative literature which a layman like me would understand about 25% of?
Interesting: If you still don’t understand what is so special about Maxwell, just compare GK107-450 to GM107-300. Both GPUs will most likely consume the same amount of power, but GM107 has twice as much CUDAs.
LiXiangyang
Newcomer
Judging by the "CUDA density" on GM107, it is not hard to expect a 20nm GM110 is likely to accomodate ~6500 CUDA cores (thats based on the assumption that they dont try to fit in a nonsense denver/ARM cores into their high end Maxwells).
At least they keep the cuda core counts in each SM the same as Kepler family, and possibly keep SMEM(despite the rumor says otherwise which I doubt)/regs/instruction issue units the same as Kepler as well, save some work on tunning and optimizing current codes for upcoming Maxwell.
At least they keep the cuda core counts in each SM the same as Kepler family, and possibly keep SMEM(despite the rumor says otherwise which I doubt)/regs/instruction issue units the same as Kepler as well, save some work on tunning and optimizing current codes for upcoming Maxwell.
Considering Dally speculated a dragonfly for the hypothetical exascale machine: http://forum.beyond3d.com/showpost.php?p=1825220&postcount=673 for 2017 I'd say that we still have time until we see as sophisticated interconnects. Is it even clear how the interconnect in current architectures looks like?
Did you also count 64 FP64 units per SMX in that math? Because anything GM10x obviously will be limited again to just a fraction of FP64 units compared to the top dog.
A1xLLcqAgt0qc2RyMz0y
Veteran
Why would Denver 64-Bit Custom ARM be nonsense in the very high-end?
It would seem like that is where it will make the most sense.
Even if the number of CUDA cores are reduced that is more than made up (and probably greatly exceeded) by replacing an Intel CPU with another GM110.
yes
like a broadcom videocore's remote procedure call
Open ARM GPU drivers
Reverse engineering power management on NVIDIA
GPUs - A detailed overview
like a broadcom videocore's remote procedure call
Open ARM GPU drivers
Reverse engineering power management on NVIDIA
GPUs - A detailed overview
The entire point of the Denver cores is to allow you to avoid having to transfer stuff over the PCIe, since you would pretty much directly port the CPU portions over to running on the Denver cores.
