xbox360 gpu explained...or so

[tEd]

http://www.hardocp.com/article.html?art=Nzcx

Frankly it didn't really answer one question i had but raised some additional ones..

 

[Jawed]

Fingers-crossed that Dave will provide some insight in the next few hours!

Jawed

 

[gordon]

Yes, the 10MB of Smart 3D Memory can do 4X Multisampling Antialiasing at or above 1280x720 resolution without impacting the GPU

So it can do 4xAA at 720p with virtually no performance hit at all?

 

[Demirug]

Yes, the 10MB of Smart 3D Memory can do 4X Multisampling Antialiasing at or above 1280x720 resolution without impacting the GPU

So it can do 4xAA at 720p with virtually no performance hit at all?

No, because AA always need some additional fillrate and shaderpower. It depends on the number of pixel with edges.

But smart Memory will save the additional bandwith that you need for AA. Alpha blending is some other thing that need less bandwith if you have smart memory.

 

[rwolf]

Well TechReport spills the beans.....

http://www.techreport.com/etc/2005q2/xbox360-gpu/index.x?pg=1

 

[hkultala]

Yes, the 10MB of Smart 3D Memory can do 4X Multisampling Antialiasing at or above 1280x720 resolution without impacting the GPU

So it can do 4xAA at 720p with virtually no performance hit at all?

No, because AA always need some additional fillrate and shaderpower. It depends on the number of pixel with edges.

But smart Memory will save the additional bandwith that you need for AA. Alpha blending is some other thing that need less bandwith if you have smart memory.

he said "with virtually no performance hit"

I'd say it's splitting hairs to start complaining about extra rendering of those (about 1%?) pixels that are edge pixels, when the question was not "absolutely not any more" but "virtually not any more"

 

[Jawed]

Well TechReport spills the beans.....

http://www.techreport.com/etc/2005q2/xbox360-gpu/index.x?pg=1

It looks like an ALU is 4D. So a vertex shader can't co-issue a 4D and a scalar operation.

I suppose if vertex shading is always going to be a relatively light load this will work out OK.

192 ops per cycle in NVidia terminology.

Jawed

 

[AlNom]

192 ops per cycle in NVidia terminology.

Jawed

a.k.a. Ati is teh win

 

[tEd]

On chip, the shaders are organized in three SIMD engines with 16 processors per unit, for a total of 48 shaders. Each of these shaders is comprised of four ALUs that can execute a single operation per cycle, so that each shader unit can execute four floating-point ops per cycle.

Sounds thay can have flexible co-issue of ops or do i read it wrong? That's where the 96billion shader ops/cycle may come from

 

[CJ]

Yes, the 10MB of Smart 3D Memory can do 4X Multisampling Antialiasing at or above 1280x720 resolution without impacting the GPU

So it can do 4xAA at 720p with virtually no performance hit at all?

No, because AA always need some additional fillrate and shaderpower. It depends on the number of pixel with edges.

But smart Memory will save the additional bandwith that you need for AA. Alpha blending is some other thing that need less bandwith if you have smart memory.

1% - 4% performance hit with 4xAA according to ATi in the Firingsquad article:

FiringSquad: You said earlier that EDRAM gives you AA for free. Is that 2xAA or 4x?

ATI: Both, and I would encourage all developers to use 4x FSAA. Well I should say there’s a slight penalty, but it’s not what you’d normally associate with 4x multisample AA. We’re at 95-99% efficiency, so it doesn’t degrade it much is what I should say, so I would encourage developers to use it. You’d be crazy not to do it.

http://www.firingsquad.com/features/xbox_360_interview/page4.asp

 

[Jawed]

The 2-terabit (256GB/sec) number comes from within the EDRAM, that’s the kind of bandwidth inside that RAM, inside the chip, the daughter die. But between the parent and daughter die there’s a 236Gbit connection on a bus that’s running in excess of 2GHz. It has more than one bit obviously between them.

So not in agreement with Dave's suggestion of a 256GB/s connection between parent and daughter.

Additionally, is this full-duplex 236Gb/s?

I wonder if that's a typo for 256Gb? The latter is 32GB/s, of course, which is in agreement with the leak.

Jawed

 

[Jawed]

This Firing Squad interview is GREAT!!!

ATI: Yeah I really think it’s just an accident because, well you know, last summer they had to change their plans. They found out that Cell didn’t work as well as they wanted to for graphics. Remember originally you had two or three Cell processors doing everything and then in August last year they had to take an NVIDIA PC chip. And as you know, all PC chips do this, and so it [dual HD display outputs] just came for free.

Class!

Jawed

 

[Geo]

I wonder how those two dies get married up? Could a die come from, say TSMC, and then get married to a NEC die at NEC, for instance? What are the nitty-gritty techie details of how the interface between the two dies works? I'm not always interested in that kind of detail, but this one does interest me.

 

[Geo]

so it allows you to do things like higher order surfaces for real this time

Somewhere inside ATI, somebody just winced.

 

[Geo]

Microsoft owns the IP

Not even "co-owns"? ATI is licensing it back or something? Otherwise forget seeing any of this in R600. Inartful phrasing, one hopes?

 

[Kaizer]

Microsoft owns the IP

Not even "co-owns"? ATI is licensing it back or something? Otherwise forget seeing any of this in R600. Inartful phrasing, one hopes?

As far as I've gathered, Microsoft owns the chip design this time 'round, so they can choose where to manufacture chips and control costs. Last time, they only ordered the actual chips, and we all remember how that turned out..

Dunno what that means for ATi's rights to develop the architecture further, though.

Kind regards
Kjetil

 

[Dave Baumann]

ALU's are 5D - Vec4+Scalar

 

[tEd]

ALU's are 5D - Vec4+Scalar

how you explain this sentence then?

On chip, the shaders are organized in three SIMD engines with 16 processors per unit, for a total of 48 shaders. Each of these shaders is comprised of four ALUs that can execute a single operation per cycle, so that each shader unit can execute four floating-point ops per cycle.

If it were 5D that would give you 5 floating point operation per cycle per shader right?

It's all very confusing :?

 

[Dave Baumann]

I would say that its incorrect (bear in mind all this is coming out in little dribs and drabs at a very busy show).

 

[tEd]

I would say that its incorrect (bear in mind all this is coming out in little dribs and drabs at a very busy show).

yes i agree there is alot of conflicting information but thanks for the clearing it up peace by peace