Megadrive1988
Veteran
Urian said:I was thinking this morning about the X2 CPU (or Xenon CPU) and it could be.
The Power5 CPU is a Server-CPU composed by:
-4 Cores at 3Ghz that supports Mutithreading.
-38MB Cache L3.
-Cache L3 is the 50% of the chip area.
-The chip area has a size around of 400mm.
If you take the 38MB cache L3 you have a 200mm 4 cores, but you can change one of the cores for 3 VMX units and you can mantain the bus channel of the L3 Cache of Power5 for the direct transfer between ATI GPU and IBM CPU.
This is my idea of Xenon CPU.
I don't think Xenon CPU will have any L3 cache at all. and I would be extremely happy to see even 2-3 MB of L2 Cache instead of the reported 1 MB.