Wii U hardware discussion and investigation *rename

[stiftl]

IBM density for eDRAM is 11Mbits/mm^2, PowerPC 470S single core is 3,7mm^2 and 512KB of L2 Cache are 5mm, in 60mm of space. If the CPU is a triple core with 512KB per core then the free space for eDRAM becomes 33,9mm^2. This means that the system can include 372Mbits of eDRAM in that space or in other words 46,5MB of eDRAM for the entire system.

32MB should be enough for 1280x720+FP16 rendering and MSAAx2, leaving 14.5MB for cache uses of the AMD GPU.

For comparison, 1T-SRAM density @45nm (Source: Wikipedia)

1T-SRAM: bit cell: 0.15 mm²/Mbit > 6,7 Mbit/mm²
with overhead: 0.28 mm²/Mbit > 3,5 Mbit/mm²
1T-SRAM-Q: bit cell: 0.07 mm²/Mbit > 14,3 Mbit/mm²
with overhead: 0.14 mm²/Mbit > 7,1 Mbit/mm²

In other words, they can use ~8 times the memory on the same die space as the original Wii. Wii had 3MB embedded, so this would already be 24MB for the same price. Doesn't seem too unrealistic

Is it really likely that they will completely drop 1T-SRAM? Isn't it much faster than eDRAM? And what about BC? Wii uses 27MB of 1T-SRAM. This embedded together with 4-6 MB of eDRAM for the CPU could do the deal, no?

EDIT: I found this info on IBM eDRAM "The 1Mbit eDRAM macros used in the POWER7 are 0.24mm2". This would only be 4,2 Mbit/mm², where did you get the 11 Mbit from?
Source: http://realworldtech.com/page.cfm?ArticleID=RWT021511004545&p=3

 

[Urian]

For comparison, 1T-SRAM density @45nm (Source: Wikipedia)

1T-SRAM: bit cell: 0.15 mm²/Mbit > 6,7 Mbit/mm²
with overhead: 0.28 mm²/Mbit > 3,5 Mbit/mm²
1T-SRAM-Q: bit cell: 0.07 mm²/Mbit > 14,3 Mbit/mm²
with overhead: 0.14 mm²/Mbit > 7,1 Mbit/mm²

In other words, they can use ~8 times the memory on the same die space as the original Wii. Wii had 3MB embedded, so this would already be 24MB for the same price. Doesn't seem too unrealistic

Is it really likely that they will completely drop 1T-SRAM? Isn't it much faster than eDRAM? And what about BC? Wii uses 27MB of 1T-SRAM. This embedded together with 4-6 MB of eDRAM for the CPU could do the deal, no?

EDIT: I found this info on IBM eDRAM "The 1Mbit eDRAM macros used in the POWER7 are 0.24mm2". This would only be 4,2 Mbit/mm², where did you get the 11 Mbit from?
Source: http://realworldtech.com/page.cfm?ArticleID=RWT021511004545&p=3

Sorry, it was a mistake from my part because I misread this:

"The overall density for the 32nm eDRAM arrays was not disclosed but should be >11Mbit/mm2 density, based on a previous paper at VLSI Symposium."

My mind made a slip and didn´t pay attention to the 32nm part.

 

[wsippel]

Where does this info come from? I hear it the first time!

Said engineer is the source. I won't provide a link, as that would disclose the guy's name as well, and could get him in trouble. There's nothing else there, anyway. All that's stated is that it's an SoC, to be released in 2012, and development work started more than two years ago.

 

[stiftl]

What size are Llano's "Stars" cores? I know they are already at 32nm but just to get an idea.

 

[Heinrich4]

What size are Llano's "Stars" cores? I know they are already at 32nm but just to get an idea.

Llano here says 228mm^2 total(stars 1/2 of this size?),if not my mistake:

http://www.anandtech.com/Show/Index...-notebook-review-a-series-fusion-apu-a8-3500m


http://www.xbitlabs.com/articles/cpu/display/amd-a8-3800_2.html


" However, the similarity in semiconductor die characteristics between Llano and Sandy Bridge doesn’t really mean anything. These processors have dramatically different distribution of the “transistor budget”. While Intel product is just a CPU with an integrated graphics core, which occupies no more than 20% of the die, AMD Llano has its graphics core under much greater emphasis. Therefore, it takes up as much space on the processor die as four processor cores combined."

 

[stiftl]

Judging by this picture a Stars CPU core alone is about 10mm², which is 3x times bigger than a PowerPC 470S core @45nm. So it seems perfectly possible that it will use at least a Llano class GPU if it will in fact be a SOC. Together with a large amount of eDRAM/1T-SRAM (say ~32MB) and 1-2GB DDR3 1500 this could be quite powerful (in comparison with PS3/XB360).

EDIT: A Turks GPU (Radeon 6570/6670) with 480SU / 24TE / 8ROPS has a die size of 118 mm² @40nm, the often speculated RV740 Radeon 4750 (640/32/16) is 138mm² @40nm as pc999 wrote. So if we keep Urians speculated triple core PowerPC 470S (~34 mm²) + 27MB 1T-SRAM(~61,5 mm²) + 6MB eDRAM (11,5 mm²) this would make an estimated die size of 225mm². This is around the size of the quad core Llano (228mm²) in Turks form and a little smaller than the 45nm Core i quadcores (263 - 296mm²) and AMD Phenom II X3/X4 (258mm²) in RV740 form (+20mm²).

EDIT 2: Forgot about memory controller(s), I/O, ... but it should fit a Phenom II budget nonetheless

In fact we still know nothing: The graphics core could be everything from 320/16/8 in the smaller Llano to 640/32/16 in the RV740. But it's fun to speculate

 

[function]

The IBM press release hinted at a single chip CGPU (probablymaybe), as did maybeperhaps the presence of IBM fab info but no ATI/GPU fab info.

The two separate intakes on the side of the WiiU case hints at a separate CPU and GPU or, alternatively, it doesn't and is simply a way to draw air from one side of the case over a single heatsink (laid across the case like in the Wii) using a rear mounted case fan.

The 5cm case fan is the same as for the GC, and total air intake area is roughly the same. The GC drew less than 30W at the wall (about 23 as far as the internets will reveal to me).

 

[Gubbi]

Is it really likely that they will completely drop 1T-SRAM? Isn't it much faster than eDRAM?

1T-SRAM is essentially eDRAM with a SRAM interface. Density should be similar, so is performance.

With 27 MB eDRAM backwards compatibility would be made a lot easier. In 'Wii mode' they can emulate the framebuffer eDRAM as well as the fast 24MB 1T-SRAM main memory of the GC/Wii. In 'Wii U mode' the on die eDRAM could hold a fair amount of render targets for 1280x720 rendering.

Cheers

 

[stiftl]

With 27 MB eDRAM backwards compatibility would be made a lot easier. In 'Wii mode' they can emulate the framebuffer eDRAM as well as the fast 24MB 1T-SRAM main memory of the GC/Wii. In 'Wii U mode' the on die eDRAM could hold a fair amount of render targets for 1280x720 rendering.

That is exactly what I was talking about! But my question keeps if the different interface between 1T-SRAM and IBM's eDRAM could make problems regarding the BC?!

 

[bomlat]

The problem is the texture cache.
It has a 512 bit wide data bus for one megs, so if it is uniform for the whole cache then we talkina about 320meg/sec bandwith,at minimum.
And from the other side the latency has to be less than 5 ns.

 

[stiftl]

The problem is the texture cache.
It has a 512 bit wide data bus for one megs, so if it is uniform for the whole cache then we talkina about 320meg/sec bandwith,at minimum.
And from the other side the latency has to be less than 5 ns.

So a 1T-SRAM for GPU / eDRAM for CPU solution is more likely?

 

[AlexV]

The problem is the texture cache.
It has a 512 bit wide data bus for one megs, so if it is uniform for the whole cache then we talkina about 320meg/sec bandwith,at minimum.
And from the other side the latency has to be less than 5 ns.

Is there a handy translation around? I'm having serious trouble figuring out what you're trying to say, but it's probably my fault.

 

[stiftl]

Is there a handy translation around? I'm having serious trouble figuring out what you're trying to say, but it's probably my fault.

I think he means that 1MB of Wii's 3MB embedded 1T-SRAM (the texture cache) is on a 512 bit wide bus, which would result in a bandwidth of 320GB/sec for the whole eDRAM in case it would be unified (which is really really fast). But I don't get the number either, what frequency did you have in mind to come to this conclusion?

As I understood the eDRAM of the Xbox360 is located on a seperate die (as are the 24MB 1T-SRAM main ram of the Wii) and so the bandwidth from GPU <-> eDRAM is "only" 32GB/sec while the bandwidth between eDRAM logic and memory is 256GB/sec. If the eDRAM/1T-SRAM of the WiiU would be located on the same die, would this mean that they could use the full bandwidth of 256GB/sec (supposing same frequency of 500 MHz)?

 

[AlexV]

...320meg/sec...(which is really really fast)...

Unless we're somewhere back in the 70s-80s, that's not really fast. Quite the opposite. You can get that from an SSD these days. It'd be orders of magnitude slower than even the DRAM included by Ninty. It doesn't make much sense. How many bits in such a meg?

 

[stiftl]

Unless we're somewhere back in the 70s-80s, that's not really fast. Quite the opposite. You can get that from an SSD these days. It'd be orders of magnitude slower than even the DRAM included by Ninty. It doesn't make much sense. How many bits in such a meg?

Sorry, I confused megs with gigs But I guess so did bomlat!
I edited it in my post.

 

[bomlat]

Is there a handy translation around? I'm having serious trouble figuring out what you're trying to say, but it's probably my fault.

Sorry,I just told half of the story.
The flipper GPU in the GC has 1 megs of texture memory,and 2 megs of frame buffer memory.
The 1 megs of texture memory has 512 bit wide bus,and it has 10.4 GB/s oops bandwidth,with 5-6 ns latency.
So,if they want to design an unified memory space for the wiiu,then every megs of memory has to have 512 bit wide bus( 16384 bit wide bus over 32 megs) ,or they can't use the full memory (if the whole unit has 2048 bit wide bus,then in GC/WII mode it will see only 1+2+16 megs of memory).
So,there is many question.either they have to go for an uber-brutal GPU design (32 megs of on-die edram ,witd 300+ G//sec bandwidth),or they have to make same compromise in the design.

 

[AlexV]

Sorry,I just told half of the story.
The flipper GPU in the GC has 1 megs of texture memory,and 2 megs of frame buffer memory.
The 1 megs of texture memory has 512 bit wide bus,and it has 10.4 GB/s oops bandwidth,with 5-6 ns latency.
So,if they want to design an unified memory space for the wiiu,then every megs of memory has to have 512 bit wide bus( 16384 bit wide bus over 32 megs) ,or they can't use the full memory (if the whole unit has 2048 bit wide bus,then in GC/WII mode it will see only 1+2+16 megs of memory).
So,there is many question.either they have to go for an uber-brutal GPU design (32 megs of on-die edram ,witd 300+ G//sec bandwidth),or they have to make same compromise in the design.

Hmm. The latency seems quite off, especially since it's eDRAM, with that size and considering how a texture cache works. Also, since we've discovered columns, rows, latches and such things, I'm at a loss with regards to why one would have to wire every single MB of memory to its discrete bus...except for amusement? The rest holds less water as well. Perhaps becoming somewhat more acquainted with how these things work would help? Or maybe there's a language barrier...

 

[kagemaru]

Nothing I wrote was speculation. It is not really a new core.

If this is true, I wonder why they said it was "impossible" for Wii games to be upscaled when played BC on the Wii-U. They would have to do some work on getting Wii games to run on a modified version of the Wii core, especially with a much newer GPU. Why not go all the way and upscale the games while they are at it?

 

[function]

Perhaps the WiiU doesn't have a 360 style output scaler. If running in Wii mode meant the edram was allocated for specific purposes, there may not be enough video memory to run at a higher resolution or upscale to a higher resolution before output either.

If the WiiU uses some/all fixed hardware modes for BC rather than a software emulator it might just be the way things are.

The 360's output scaler has been a godsend. Whoever decided to put it in deserves a Nobel Prize for services to video games.

 

[kagemaru]

Perhaps the WiiU doesn't have a 360 style output scaler. If running in Wii mode meant the edram was allocated for specific purposes, there may not be enough video memory to run at a higher resolution or upscale to a higher resolution before output either.

If the WiiU uses some/all fixed hardware modes for BC rather than a software emulator it might just be the way things are.

The 360's output scaler has been a godsend. Whoever decided to put it in deserves a Nobel Prize for services to video games.

Oh ok, I always thought AMD GPUs have had similar, if not better, scaling capabilities even before Xenos. Swore I read that somewhere, but don't remember where. Thanks.