What are the advantages of multi-chip cards?

[BoddoZerg]

Then we'd be looking at 1PB/sec... even 1EB/sec. Ouch. Thinking about a card with 1EB/sec memory bandwidth... woo...

What's the point of 1 EB/sec of memory bandwidth? Once you get so many orders of magnitude beyond what we have now, simply scaling up the stuff we have now (multitexturing, bump mapping, pixel shaders, per pixel lighting etc) will reach diminishing returns because there's just not that much detail you can render. Beyond that, you'd be talking about global illumination, which is like factoring gargantuan prime numbers - its intractable for classical technology, you need quantum computers to make it a tractable problem. Dunno how you'd measure the memory bandwidth of a quantum videocard, does Qbits/sec actually scale linearly in the same way that bits do?

 

[Dio]

Also there is the resolution question. There's no great need to go beyond 1600x1200, unless there is some big leap in display technology soon.

I don't really forsee things going much past 16x12 with 16X AA... I know, never say never, but the 'push' to go higher is really going to slow.

 

[BoddoZerg]

Also there is the resolution question. There's no great need to go beyond 1600x1200, unless there is some big leap in display technology soon.

I don't really forsee things going much past 16x12 with 16X AA... I know, never say never, but the 'push' to go higher is really going to slow.

IMHO, at the rate technology is advancing now, within a few years virtually everything will be renderable at 16*12 with at least 4x AA and 8x AF. The rate at which Plasma Screens and other super-high-resolution display devices become widely available is certainly going to be much slower than the rate of computer graphics development. Thus, once resolution and texture detail (which is limited by resolution) are maxed out, the greatest improvements in visual quality are likely to come from lighting techniques; soft shadows and light bleeding seem to be very difficult to do properly on today's hardware but are essential for a realistic looking scene.

 

[Tagrineth]

I dont think you can just think more is better with this...
The 20GB/s of the 9700 is anough for 2+ texture layers at 1600*1200 with 16x adaptive anisotropic at 100fps.
If you go to 10 texture layers ( why would you need that? ) and 1024x anisotropic limit in 3200*2400 i think you wont even use 1TB/sec
The higher the anisotropic the less pixels it does ... i think at 64x it probably does less then 1% of the pixels, at 1024x maybe 100pixels left on whole the screen.
So this is why im pretty sure that for texture bandwidth 1TB/sec would be anough to do perfect texture calculations with.
The other things can be saved on chip ram in the future and i dont even think they use as much bandwidth.
If anything would use more bandwidth eventualy it wouldnt even mather because its on chip ram, this 1TB/sec is just for the texture memory because they would take to much space on the chips.

I wasn't thinking of it as pure texture memory. I was thinking unified frame buffer.

If that much bandwidth is available, supersampled AA would be viable, and I'm sure we all want that but of course supersampling takes a LOT of extra frame bandwidth so...

Oh well, doesn't matter in the end.

 

[Dave B(TotalVR)]

Would this be a good point to bring up how PowerVR technology could scale near perfectly with multiple chips?


You have a tile processer which throws out ready to render tile data to an array of x image synthesis processers, this tile processer wont actually have that much logic on its own (its always been integrated on the PowerVR based chip) so it will be able to be clocked bloody high.

All the tile processer needs to do is feed a small buffer (say 5 tiles worth) that sends the current tile to the next ready image synthesis processer. This whole thing is possible because we are dealing with 32x16 tiles. All each chip needs is a bus to the texture memory, the tile proc can even get the texture information prefectched for each tile that comes along.

/me stops shamelesly plugging powervr

 

[arjan de lumens]

There seems to be a widespread idea around here that larger chips necessarily clock slower than smaller chips - where does this idea come from? Especially given that available evidence seem to indicate a weak tendency in the opposite direction (R300 vs NV2x, Pentium4 vs AthlonXP)

 

[flf]

Ah, but what speeds would all those older cores run at if produced at .13? (Assuming you modified the chips to time correctly on the newer process.)

Granted, they wouldn't just scale infinitely, but they would probably be capable of a bit more speed. I imagine the biggest problem is the usual problem with speed... more speed means deeper pipelining and more caching/buffering.

 

[arjan de lumens]

If you assume linear scaling of performance with transistor feature size (which is a bit optimistic), at 0.15 micron the TNT2 would end up at 175*0.25/0.15 = 292 MHz and the Geforce2 Ultra would end up at 250 * 0.18/0.15 = 300 MHz, both falling short of the much larger 9700Pro at 325 MHz - still seems to support the observation that larger designs don't normally clock any slower than smaller designs when the process feature size is kept constant.

 

[RoOoBo]

The only reason the frequency would be affected by the die size is power. The more transistors the more power you are using (usually). However in current CPUs most of the transistors (die area) is cache which is low power compared with the CPU core, so it depends how this area (transistors) is used.

Frequency is determined by the size in gates of the largest stage in the pipeline, the gate frequency change at a given voltage/technology and how much power is dissipationg the die.

 

[KimB]

Would this be a good point to bring up how PowerVR technology could scale near perfectly with multiple chips?

You have a tile processer which throws out ready to render tile data to an array of x image synthesis processers, this tile processer wont actually have that much logic on its own (its always been integrated on the PowerVR based chip) so it will be able to be clocked bloody high.

Would work well, but only if you also had one or more T&L/vertex processors as separate chips. Basically, it could be viable for the very high-end, particularly for offline rendering, but not so much for a consumer product.

Of course, move everything onto one chip, and it becomes better for a consumer product, but there's still the question of the worst-case performance of a deferred renderer.

 

[Nappe1]

Having a multi-chip solution would make it easier to scale across dif markets. Single chip for budget gamers, dual config for mid-range and quad setup for enthusiasts. You get the idea.

Fuz

rip the quad off, and you gotcha egg that was made, but never turned to be as chicken...

when?? I would say that if something would happened, it would happened between August 2001 and December 2001. but as wen knew already in November 2001, it didn't make it.