Understanding Litho-Process Partnerships

[Carl B]

Now here's a favorite topic of mine - the lithography processes behind all our favorite chips.

Specifically here, I'm wondering what the deal is - the interplay if you would - between all of these various chip companies that have R&D agreements with each other. How transparant are advances made with one partnership allowed to be to partners in another, 'on the side' partnership?

Specifically, let me outline several modern partnerships here:

IBM & AMD 45nm

STI on 32nm

Sony, Toshiba, NEC on 45nm

Now these actually are pretty bad examples for the subject I'm discussing, because they actually do not conflict directly with one another... but AMD/IBM/Chartered's recent 65nm work vs STI's 65nm work would be one such example. If the STI crew comes up with something, can IBM take it into the meetings with AMD? And likewise on the reverse. Will the immersion lithography process refined on 45nm with AMD and IBM be translated wholesale to 32nm for Toshiba and Sony when that time comes? Really I'm just wondering to what extent 'partnership' advances are kept within the respective families.

And speaking of Cell on 32nm, maybe it'll help to create itself?

(off topic but fun anyway)

excerpt

...To deal with this, all kinds of compensating factors (called Optical Proximity Correction, or OPC) have to be encoded into the "mask design" stage. These additions look like bumps, unusually shaped squares, lines placed out of place, and other techniques that are required to physically "trick" the light into going where it's supposed to go.

These OPC requirements introduce much greater complexity to the design stage and significantly increase validation time. An OPC database might be 500 MB at 180 nm, taking only a few hours to compile. Drop down to 65 nm feature sizes and the OPC database increases 1,000 fold to 500 GB, taking (literally) months of processing time to compile (but it's done in parallel, so it's completed more quickly in real time). These extreme compensating factors allow the mask to then, even with the distortions, produce correctly shaped features because of the OPC additives...

excerpt

... Hardware acceleration techniques are increasingly implemented in specialized applications that require more processing power than mainstream solutions can offer. The novel platform combines a standard compute cluster with the Cell BE processor to cost-effectively deliver up to a 20x increase in compute capacity and speed now required for resolution enhancement tool (RET) applications at and below 45nm.

The amount of computation required to complete the 45nm and below RET flow has increased dramatically compared to that of the 65nm node. Larger devices, larger optical diameters, more model kernels, through-process simulation, and more compute-intensive process modeling have pushed computation requirements for the 45nm node from 5 to 20 times that of the 65nm node. Even if critical layer jobs can complete on standard farms, the turn-around time (TAT) is unacceptable, and the number of CPUs and licenses are too costly. In addition, companies moving to 45nm want to preserve their current hardware investment. It has become clear that software innovation is needed to address all of these issues in tandem with a new, innovative HPC platform...

 

[mesyn191]

Can't find it anymore but there were posts by PD on RWT about this last year, Sony's, IBM's, AMD's, and others processes will be related to each other but all heavily "tweaked" for their specific purposes sometime around when they start to go 45-32nm or so IIRC. So they'll have lots in common but being able to swap tech. will still be no easy and/or straight forward thing so assumptions still could not be made about the others' processes based on info. we get about one.

 

[ADEX]

Now here's a favorite topic of mine - the lithography processes behind all our favorite chips.

Specifically here, I'm wondering what the deal is - the interplay if you would - between all of these various chip companies that have R&D agreements with each other. How transparant are advances made with one partnership allowed to be to partners in another, 'on the side' partnership?

IBM & AMD 45nm

STI on 32nm

Sony, Toshiba, NEC on 45nm

Really I'm just wondering to what extent 'partnership' advances are kept within the respective families.

Good question but these partnerships tend to be for specific processes, e.g. High performance, low power or bulk. I'd imagine there is some degree of sharing tech though, if an IBM guy comes up with an idea I'd imagine IBM can use it in other projects.

And speaking of Cell on 32nm, maybe it'll help to create itself?

What I thought even better was the thought of Cell being used to create AMD or Intel processors, don't think they'll be keen on admitting it though!

 

[Carl B]

Good question but these partnerships tend to be for specific processes, e.g. High performance, low power or bulk. I'd imagine there is some degree of sharing tech though, if an IBM guy comes up with an idea I'd imagine IBM can use it in other projects.

I don't doubt that there is some tech sharing, which is sort of what prompted this in the first place. I agree the partnerships by their natures target different things (ie bulk, SOI, etc...), but that is in part a factor in my curiosity. For example Sony, NEC, and Toshiba's bulk 45nm efforts are likely altogether a seperate 'thing' from AMD and IBMs 45nm efforts - though both target immersion lithography - but come STI 32nm Cell time, will that lithograohy tech and knowledge be pooled between the three? Or will AMD and NEC respectively be able to flag aspects that must be held back?

Also with the Cell development STI partnership at 65nm, Sony has picked up the silicon-on-insulator expertise needed to open their own SOI line at Nagasaki. Toshiba however is pursuing a low-power bulk process at that node, and I wonder - did IBM factor in to that research? It's not normally their thing these days. Is that aspect of Cell fabrication something Sony and Toshiba pursued completely on the side, as part of their CMOS bulk R&D agreement?

You know... not that any of this is material in our day to day discussions, but just whenever possible, I like to have an understanding of the business side of these technology dealings.

@Mesyn191: Thanks for those node insights, now I have to try and do some Googling. I suppose the base similarities likely relate to common pursuit of immersion lithography by both the AMD/IBM alliance and the Sony/Toshiba/NEC alliance.

 

[3dilettante]

I think it's an interesting reflection of the cost of further scaling that we see partnerships between companies that would probably like to go it alone.

For another reason for this collaboration, notice that there is one big chip firm that so far hasn't been mentioned...