TSMC to make chips for next Xbox

[Megadrive1988]

We know nothing about the cpu for the xbox and process it will be on.

I thought that was confirmed to be on IBM's 65 nm ?

maybe not then...

 

[Megadrive1988]

back on-topic, regarding the GPU/VPU:

Nexsys is the brand name that TSMC has given to its most advanced process technologies, including the 90-nanometre process that is currently in pilot production and its 65-nanometre process, which is still in development.

The most advanced process technology used by TSMC for commercial production is its 130-nanometre process.

A spokesperson for TSMC in Hsinchu, Taiwan, J.H. Tzeng, declined to comment on the specific process that would be used to make the Xbox chips.

He did not disclose whether the SOCs that TSMC will produce would be designed by Microsoft or another company.

If the Xbox chips are made using a 65-nanometre process, that would match the technology that Sony plans to use for production of its Cell microprocessor, which will be used in the company's PlayStation 3 game console.

While the first generation of the Xbox mainly uses off-the-shelf PC components, Microsoft has taken a more active role in the development of chips for the next generation of its game console.

In November, the company announced that it had signed technology licensing deals with several companies, including graphics chip vendor ATI Technologies, chipset vendor Silicon Integrated Systems and IBM, which makes the Power PC processor. Those licensing agreements enable Microsoft to incorporate technology from these companies into SOCs for the next generation of the Xbox.

whole article:
http://www.pcworld.idg.com.au/index.php/id;1329352102;fp;2;fpid;1

 

[jvd]

We know nothing about the cpu for the xbox and process it will be on.

I thought that was confirmed to be on IBM's 65 nm ?

maybe not then...

I don't remember ever reading it will be on 65 nm process . I remember reading it will be fabbed by ibm though

 

[Wunderchu]

http://www.anandtech.com/news/shownews.html?i=21932

 

[Vince]

well if you want to get into . All we know is that the xbox 2 gpu will be done at tmsc and they should have 90nm or perhaps an early 65nm .

We know nothing about the cpu for the xbox and process it will be on. Which makes this whole arguement moot.

No it doesn't. We can have a discussion based on the relative capabilities of each process and the movement in time based off what TSMC is offering - how did you arrive at this conclusion?

I'm guessing the same way that the movement from 90 -> 65 was small

Yet, you continue to talk about clockspeed and the same, tired, arguments about nVidia and ATI. Clockspeed is going to be influenced by not only implimentation details and construct design, but process technology (like Low-K or SOI) and so many variables, you can't make the argument you are.

Same tired arguements ?

Nvidia used a smaller micron process .

They had horrible yields and needed a higher clock speed to put a similar performing part on the market compared to ati .

Not only that but the nvidia part had a bigger transistor bugedt than ati.

So in conclusion . A smaller micron process for nvidia while being able to use more transistors and get a cooler performing chip which in theroy should allow it to clock higher acomplished none of those things/

Did you not read my post? My post still stands and basically answers every day thing you attempted to say here. nVidia's problems, as time has shown, stem from more than just the inherient process. nVidia designed a part against TSMCs warnings about the early yeilds, they then suffered problems after the Low-K dielectric problems and they failed to fully utilize the process - all of which I mentioned.

So, in conclusion, nVidia is to blame. Not the process itself - which would be absolutely asnine to state. ATI sure as shit didn't have problems with their ICs using the 130nm Low-K process, explain that one. I find it embarrasing that you're even using this argument yet again...

which means at 65nm the cell chip may not clock to reach thier goals . May run extremly hot and may not over a performance increase of what they are expecting over other chips.

What part of the influx in logic because of transistor budget do you not understand yet? Preformance != Clockspeed. Especially on 3D Architectures, this is like arguing against a wall.

They expect it to perform like that . Do they expect it to perform like that right off the bat .

Well i doubt it .

And going by your above comments, you're in a great position to state this so definitively.

 

[nondescript]

Long time no post.

Anyways:

http://www.eetimes.com/semi/news/sh...id=P14RQDERWRWUMQSNDBGCKHY?articleID=18900667

TSMC readies new business strategy
By Anthony Cataldo
EE Times

SAN JOSE, Calif. — Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) next week will unveil a revamped business strategy meant to take on the increasingly difficult task of designing, manufacturing and testing advanced semiconductor devices. At the same time, the company will announce that it has manufactured its first 65-nanometer test chip.

TSMC's "platform" approach, which will be announced at the company's technology symposium here next Tuesday (Aril 13), is meant to address the disconnect between chip design and manufacturing, which has worsened in recent years with the shift to 130- and 90-nm process design rules.

The gap has been pegged as a root cause for fundamental changes that are reshaping the semiconductor industry, from a decline in the number of full-custom chips being designed to the scarcity of venture capital funding for startup chip companies.

At past symposia, TSMC has weaved in suggestions about how to address design-to-manufacturing problems within the framework of discussion about process technology. This year, design-for-manufacturing will be a central theme.

"What we have done is positioned our technology and design services into a holistic approach that we call platforms," said Chuck Byers, director of brand management at TSMC. "Success is going to depend on something more than process technologies. What is required is an integrated environment for the backend, assembly, test, packaging and libraries. All that needs to be addressed up front."

The company said it has tweaked its marketing focus accordingly, appointing two senior managers to lead the platform effort. Ken Chen, who was overseeing business development for TSMC in Japan, is now director of mainstream technology platform marketing. John Wei, the former director of Fab 5 in Hsinchu, Taiwan, has been reassigned to director of advanced platform marketing.

As part of the plan, TSMC will present a new set of design guidelines for its most advanced process technologies, particularly for 0.13-micron and below. Some of the these structured design rules "are absolutely required to achieve certain yields; others are suggested for certain yields," Byers said.

The platform design strategy is being rolled out as the company prepares to disclose plans to fabricate chips based on 0.065-micron design rules. Next week, the company will announce that it has produced its first 0.065-micron SRAM module and that it plans to start making the first low-power devices at that process node by late 2005. The high speed version will be ready in the first half of 2006, followed by the general purpose process module in the fourth quarter, Byers said.

The company's most advanced chips today are based 90-nm design rules, which is slated to move into full production by the second half of this year. At the symposium, the company will also discuss technical details for its "half node" 0.11-micron process technology and new ways to support older nodes starting at 0.18-micron and greater, Byers said.

In order to succeed, TSMC is seeking more backing from third-party companies, including those developing software tools and intellectual property cores. Emphasizing this point, Synopsys chief executive officer Aart de Geus will deliver a keynote stressing the importance of moving to a more collaborative design model, Byers said.

Clearly, because of nVidia's aggressive use of advanced process nodes (including half-nodes), their yield suffered.
TSMC felt that to keep that from happening again, they had to come out with guidelines, requiring certain safety margins to guarantee yields.

Node timelines:

130 nm:
Full production now

90nm:
Full production - second half of 2004

65 nm:
SRAM modules - already made
Low power devices - second half of 2005
High speed devices - first half of 2006
General use - second half of 2006

 

[jvd]

No it doesn't. We can have a discussion based on the relative capabilities of each process and the movement in time based off what TSMC is offering - how did you arrive at this conclusion?

I'm guessing the same way that the movement from 90 -> 65 was small

Hmm we don't know what the cpu in the xbox is going to be made on .

If its ibms 65 nm process then it will have the same capabiltys as sonys 65 nm process .

Then the diffrences will be moot .

Did you not read my post? My post still stands and basically answers every day thing you attempted to say here. nVidia's problems, as time has shown, stem from more than just the inherient process. nVidia designed a part against TSMCs warnings about the early yeilds, they then suffered problems after the Low-K dielectric problems and they failed to fully utilize the process - all of which I mentioned.

You never answered anything but try to dismiss it .

How about intel you say nothing about it .

If tsmc had problems with early yields how do we know that there wont be problems on 65 nm and early yields .

It will be a very mature 90nm process vs a very immutaure 65nm process .

Which can then be compared to the r300 vs nv30 or to the willimate vs presscot .

So, in conclusion, nVidia is to blame. Not the process itself - which would be absolutely asnine to state. ATI sure as shit didn't have problems with their ICs using the 130nm Low-K process, explain that one. I find it embarrasing that you're even using this argument yet again...

sure now explain away intel

What part of the influx in logic because of transistor budget do you not understand yet? Preformance != Clockspeed. Especially on 3D Architectures, this is like arguing against a wall.

Obviously you did not read what i wrote .

Sony has goals in which they want their cpu to perform at .

Those goals will be met by the apus on chip , clock speed and die size .

If there is trouble with the process like nvidia had and later ibm had .

Thus the cell chip sony wanted will not clock as high as sony will want .

Thus if it needs to be 1ghz to reach 1tflops and they can only hit 100 mhz you can bet there will be huge problems .

Clockspeed is more than relvent when compareing with in its own tech .

And going by your above comments, you're in a great position to state this so definitively

Just looking at the past .

That transitor count may be what they expect for the process . When do they expect that goal to be met ? At launch ? A year into the process being out ?

When ?

Its just like hearing the cell chip hitting 1 tflop. Yea mabye one day it will. Will it do it with the first cell chip that is launched ? I highly doubt that .

Do you realize that, just to illuminate a What If, if I design a 'big' 90nm IC with, say, 500M transistors looking forward to cost normalization at 65nm; my competitor whose designing at a base 65nm can design a Billion transistsor IC looking towards 45nm. And what's most shocking to me is that this is for the GPU fabrication -- the area I expected MS to gain the most relative ground verse the PS3 in.

Yes and if your competitor who is designing at a base 65nm has leakage problems , heat problems , clock speed scaling problems you have nothing to worry about .

Because in a fixed process in 6 months when the problems are fixed they can't upgrade the specs . They will be screwed .

Just like what happened with nvidia . Just like what is happening with intel.


But wait . I'm talking to vince and he is defending his god . So how could i ever say anything bad about sony mhaving problems with a process .

 

[cthellis42]

Agh, that post is just huge for no apparent reason! jvd, is there some reason you don't post in paragraph form, but rather a continual string of single sentences double-spaced to the next one? It just makes reading and comprehending and quoting more annoying! I saw Baby Jesus, and he was crying... Stop the insanity!

 

[bbot]

Will IBM also make the Xbox2 cpu? If you believe TheInquirer.com got a hold of an internal IBM memo, it say IBM will also make the cpu for Xbox2.

http://www.theinquirer.net/?article=12552

 

[Megadrive1988]

I think it's pretty clear that IBM will design the Xbox 2 CPU(s) as well as manufacture / fab them. either 90 nm or 65 nm

I suppose there is some chance that AMD will design the CPU, but then there is also a chance MS will go back to Nvidia for graphics. anything is possible.

 

[Qroach]

Exactly... so why is vince arguing so much?

 

[Vince]

Hmm we don't know what the cpu in the xbox is going to be made on .

If its ibms 65 nm process then it will have the same capabiltys as sonys 65 nm process .

Then the diffrences will be moot .

This is still wrong. IBM has a tiered system of process technologies. I do believe that the STI process is a derivative of the 'xS' steping, as opposed to the 'xSF' process used with, say, UMC or Chatered or other 3rd parties.

Also, there are attributes like the SRAM, eDRAM cell which are held by Sony and Toshiba's agreements, which oviously wouldn't be used.

So, only moot in your head JVD...

Did you not read my post? My post still stands and basically answers every day thing you attempted to say here. nVidia's problems, as time has shown, stem from more than just the inherient process. nVidia designed a part against TSMCs warnings about the early yeilds, they then suffered problems after the Low-K dielectric problems and they failed to fully utilize the process - all of which I mentioned.

You never answered anything but try to dismiss it .

How about intel you say nothing about it .

If tsmc had problems with early yields how do we know that there wont be problems on 65 nm and early yields .

It will be a very mature 90nm process vs a very immutaure 65nm process .

Which can then be compared to the r300 vs nv30 or to the willimate vs presscot

I did answer it. It's nVidia's fault, as it's been widely stated. Dave Baumann stated as much AFAIK several times. What about Intel? Um, perhaps it's implimentation problems again. :ets try to be logical about this - hard to do, sure, but lets try.

Sony is shipping a 90nm, Low-K processor. Toshiba is shipping some as well. IBM is shipping 90nm IC's as well. Obviously there isn't something intrinsic in this "90nm" term which makes it equal to failure or problems. It's a technology which is used by each company to manifest their IP - if their IP is flawed or their technology is late or buggy, that's their problem. It's obviously not capable of being lumped into this massive "90nm" pool of evil which you're trying to.

Mature 90nm verse immature 65nm, wow what a choice for a console which will last untill 2010, huh?

sure now explain away intel

Their design or implimenation sucks? JVD, it can't be a process problem when companies like AMD, Sony, IBM, ATI-TSMC/UMC, et al. are all using the technologies (be them 90nm or Low-K) and using them to great success. ATI has stated in their CC that they have great yeilds at 130nm, yet nVidia has claimed to be the exact opposite - why?

What part of the influx in logic because of transistor budget do you not understand yet? Preformance != Clockspeed. Especially on 3D Architectures, this is like arguing against a wall.

Obviously you did not read what i wrote .

Sony has goals in which they want their cpu to perform at .

Those goals will be met by the apus on chip , clock speed and die size .

If there is trouble with the process like nvidia had and later ibm had .

Thus the cell chip sony wanted will not clock as high as sony will want .

Thus if it needs to be 1ghz to reach 1tflops and they can only hit 100 mhz you can bet there will be huge problems .

Clockspeed is more than relvent when compareing with in its own tech

Wow, So you've again failed to see why I told you not to comment on clockspeed like DM? How does PD-sSOI or application of a Dielectric or Power-aware architectural features or just increasing the voltage impact this?

Clockspeed, for the 3rd time, isn't dependant on just process technology.When you're talking about an architecture which is as parallel as these are, the order of their preformance will be bounded by their logic potentialities, not clockspeed.

Do you realize that, just to illuminate a What If, if I design a 'big' 90nm IC with, say, 500M transistors looking forward to cost normalization at 65nm; my competitor whose designing at a base 65nm can design a Billion transistsor IC looking towards 45nm. And what's most shocking to me is that this is for the GPU fabrication -- the area I expected MS to gain the most relative ground verse the PS3 in.

Yes and if your competitor who is designing at a base 65nm has leakage problems , heat problems , clock speed scaling problems you have nothing to worry about .

Because in a fixed process in 6 months when the problems are fixed they can't upgrade the specs . They will be screwed .

Just like what happened with nvidia . Just like what is happening with intel.

Not again. JVD, those problems are implimentation dependant to a large extent. How fucking hard is this to understand? If I never take my car out of 1st gear, does that mean that the car is only capable of that level of preformance? Of course not.

What you're doing here is an excercise in stupidity. Instead of yeilding to the obvious fact that the technologies themselves aren't flawed, and thus, some people are having sucess with it (eg. Sony and 90nm while nVidia/ATI are using 130nm), you're looking for someone who'se had a problem with it and using that example as a base for every implimentation. How much more DeadmeatGA-esque can you get?

Here's a hint. If you have one example showing it's possible, then it's possible based on solely the existence of that example. Now, sure, you can preach to the God's of insanity by stating more situational dependant What If? questions. What is the 65nm process sucks, what is the 90nm scales better that expected....

Valid questions, but just as valid as What If 65nm matures better that expected? Or What if space aliens come down to Earth, kidnap you and launch you at the Nagasaki Plant as a high-energy, ultra high velocity projectile and you destroy it all?

But wait . I'm talking to vince and he is defending his god . So how could i ever say anything bad about sony mhaving problems with a process .

JVD, it's no "God"; my "God" is the God of logic and knowledge, you should try it sometime. You're argument is based upon utterly ridiculous properties which offer up horrible, set-piece, examples which aren't reminescent of a global problem and What If questions which, while valid, are utterly useless at this time.

What if Sony has problems? Then they have problems - big deal. But they have no recent history wrt process technology to use as precedence of such a problem (which is a fact that you overlook in your bias), nor do you consider their relative preformance against the industries in contimplating these What If's? Instead of looking at what's highly probably for Sony, you just state... well, what if they have problems like Intel did or nVidia did - without actually looking at the situational contexts and knowledge we have at our fingertips. So freakin' asnine.