Theory and practice are two very different things in such a case. Look at TI: they were ahead of TSMC in terms of process node, so why exit the process race? Three reasons, two obvious and one not: economies of scale on R&D, economies of scale on manufacturing, and finally... transistor density. I don't have all the data right here, but raw gate density (which isn't that great of an indicator but is by far the best we have) was 33-75% higher at a given process node at TSMC (depending on variants etc...). When you combine that with the possibility of half-nodes, TSMC's 40nm process would trounce TI's 45nm process by a truly ridiculous amount in terms of gates/mm² and perf/$.
I doubt the difference as massive for AMD/IBM's process versus TSMC, but SRAM cell size for example is ~0.24 square micron on TSMC's 40nm node vs ~0.37 square micron on AMD's 45nm node. In terms of gate density, it's ~2080 kgates/mm² at TSMC vs ~1450 kgates/mm² at IBM. So TSMC's advantage for SRAM and gate density are 54% and 40%, respectively.
Please understand that these numbers are theoretical. They are good approximations but never perfectly comparable; generally speaking, always expect differences to be inflated. However, it should be clearly that if gate density is 40% higher, you should expect a noticeable advantage in die size for a chip manufactured at TSMC. Clock rates might be lower, but for a notebook or low-end part, that really doesn't matter much. The cost savings and higher integration potential are much more valuable.
It has nothing to do with that. SMIC is simply behind technically, so AMD would be on a modern process node there later than at TSMC, increasing average cost per transistor compared to TSMC.
Furthermore, with TSMC, that makes CPU-GPU integration easier. SMIC just makes it even harder. None of that really makes any sense; think about it.
