The AMD Execution Thread [2007 - 2017]

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Care to point out which numbers scream "superlinear"?

I'm not sure I'm reading them right.

First post of the thread, initial SPI numbers.

SPI 1M @ 2GHz = 39.750s
2.4GHz = 32.672s

20% clock increase = 19.27% perf increase.

I mis-read the initial responses to these numbers and saw some saying it was super-linear, but their math was off. So not super-linear afterall, but darn close to linear and certainly better than scaling on K8 or C2.
 
In response to the earlier disbelief about the overclockability of Phenom, I only have this to say. Independently overclockable cores, up to 3.33GHz :devilish:
 
First post of the thread, initial SPI numbers.

SPI 1M @ 2GHz = 39.750s
2.4GHz = 32.672s

20% clock increase = 19.27% perf increase.

I mis-read the initial responses to these numbers and saw some saying it was super-linear, but their math was off. So not super-linear afterall, but darn close to linear and certainly better than scaling on K8 or C2.


It's always better to believe the man himself then posters who do not know what they are looking at :D

It's good linear scaling at the moment but it will drop off as it gets higher I'd expect as bottlenecks are exposed, not bad up to now I agree.

Looks like it is 10% behind Kentsfield in 3dmark06 but hopefully with better supporting hardware it will be level or slightly ahead. Therefore it will only have to get to about 4Ghz to be competitive ......
 
In response to the earlier disbelief about the overclockability of Phenom, I only have this to say. Independently overclockable cores, up to 3.33GHz :devilish:

All we need now is some automated method of setting affinity or an update to the OS scheduler to keep compute-intensive threads on the faster cores.

As was noted, this capability is only partially utilized until the next socket transition, where independent voltage planes are added.

P.S.
I recall an Intel slide stating Penryn will have a similar capability as well.
 
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All we need now is some automated method of setting affinity or an update to the OS scheduler to keep compute-intensive threads on the faster cores.

As was noted, this capability is only partially utilized until the next socket transition, where independent voltage planes are added.

very true

P.S.
I recall an Intel slide stating Penryn will have a similar capability as well.

Link? That's news to me. Not saying it isn't true, just that I don't recall such a feature having been mentioned WRT Penryn or it's supporting chipsets. Although that would help explain the incredibly quick transition from X38 to X48.
 
Link? That's news to me. Not saying it isn't true, just that I don't recall such a feature having been mentioned WRT Penryn or it's supporting chipsets. Although that would help explain the incredibly quick transition from X38 to X48.

I was referring to what Intel calls Enhanced Dynamic Acceleration Technology.

http://www.intel.com/technology/architecture-silicon/intel64/45nm-core2_whitepaper.pdf

It may be more restrictive in practice than what has been shown tweaking Phenom, but the ability for the hardware to independently clock and automatically scale one core over the other is present.

It may end up not being the same, but I think the necessary hardware framework is already there.
 
I was referring to what Intel calls Enhanced Dynamic Acceleration Technology.

http://www.intel.com/technology/architecture-silicon/intel64/45nm-core2_whitepaper.pdf

It may be more restrictive in practice than what has been shown tweaking Phenom, but the ability for the hardware to independently clock and automatically scale one core over the other is present.

It may end up not being the same, but I think the necessary hardware framework is already there.

Perhaps Phenom-like core-clocking would be relegated to Extreme Edition parts and the Skulltrail platform, I just don't see Intel releasing software which would enable independent core-clocking for the mainstream.
 
It's inevitable that there will be some benchmarks better served by higher clock speed and larger non-shared caches.

The memory performance numbers seem very off for Phenom. Its memory divisor at 2 GHz should allow optimal performance at DDR800 speeds.
Even if the controller's design features hurt latencies a little, it shouldn't result in some of the large disparities noted.
 
Looks like it is 10% behind Kentsfield in 3dmark06 but hopefully with better supporting hardware it will be level or slightly ahead. Therefore it will only have to get to about 4Ghz to be competitive ......
It's unlikely, 3DMark06 CPU is virtually unaffected by memory bandwidth or latency.
 
So how much cheaper do you expect that 2.0GHz quad to be?

Not at all. 2.0GHz quads have their uses. The average home user certainly doesn't need one though, so if they buy one and get lower performance than a similarly-priced dual-core then its their fault for not doing their homework.
 
Phenom rumored to launch at top speed of 2.4GHz

When we covered the upcoming launch of Phenom last month, we reported that AMD's new CPU platform was rumored to launch at speeds of 2.2 and 2.4GHz at 89W TDP, with a 2.6GHz, 125W chip coming in December. Now, according to The Inquirer, AMD has scaled those plans back further, and is planning to launch CPUs at 2.2GHz (Phenom 9500), 2.3GHz (Phenom 9600), and 2.4GHz (Phenom 9700). TDP has also been increased, to 89W, 125W, and 125W, respectively. (The Inq's take on the scale-back is different from ours, as it initially reported a 2.6GHz part launching in November, with 2.8GHz in December).

Although the TDP jump is less than ideal, it doesn't strike me as indicative of all that much. AMD's published TDP numbers have always been based on the maximum theoretical draw of a given chip, not the amount of power the CPU is consumes running at full load. This one could come back to bite me, given that AMD obviously raised Phenom's TDP for a reason, but I'd still bet on the 9600 and 9700 coming in well under their 125W TDP.

As I've said before, the most important thing AMD needs to do with Phenom's launch is demonstrate that the CPU is available for purchase in OEM machines, even if it's not widely available in channel. Additional speed grades are also going to be a necessity, but given the pointlessness of paper launching higher-speed CPUs that no one can buy, I'd still put availability over clockspeed when evaluating the issues that AMD needs to address first.

http://arstechnica.com/journals/har...enom-rumored-to-launch-at-top-speed-of-2-4ghz

I guess phenon is not a great deal compared to Athlon after all.
 
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Call me cynical, but all those aspects of Phenom launch at least in part answer all the "Why in the world would Henri leave just before the K10 rollout?" questions.
 
Phenom rumored to launch at top speed of 2.4GHz

<snip>

I guess phenon is not a great deal compared to Athlon after all.

Why link to ars when all they've done is reference the Inq? That doesn't add any credibility to the rumor. As for Phenom not being a "great deal" compared to Athlon 64 X2 - where are the benchmarks that show this and the costs of each processor to perform a price: performance ratio analysis? The benches you linked earlier have already been debunked (in terms of meaningfulness anyway).
 
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