The AMD Execution Thread [2007 - 2017]

[Alexko]

And let me guess: no HBM for APUs either?
So AMD will be putting their brand new, supposedly more power-efficient cores into a dying design for the consumer market (GPU-less CPUs), and leave the APUs with the old and bad cores, together with an ancient memory controller.
And they gut their APU line's competitiveness after they've been spending money on developing HBM and preaching about the advantages of HSA everywhere.

I give up...

All they said is "DDR3/DDR4 compatibility". I guess they didn't have time to integrate Zen into APUs for 2016. As for HBM, I don't know. Too expensive?

Some of the slides are already available here:
http://edge.media-server.com/m/s/xzfr4avf/lan/en

The roadmap, if you can call it that, is on page 17: http://i.media-server.com/m/s/xzfr4avf/a/pacne5oe

 

[Alexko]

And now Forrest Norrod is trying to bore me to death, talking about what computers are useful for, even though I've never done anything to him. So I won't be watching the rest of the webcast, sorry. I doubt I'll be missing much anyway.

Aside from possibly a SeaMicro-type system, whose overall appeal appears to have been decisively measured, was there a client type that was primed to swap between chips? I don't recall.
The lines seem stark these days where going ARM means aiming a system one way, and going x86 means going another, either in terms of workload or the platforms.

AMD seems to agree with you. I don't really know what they were originally hoping for exactly.

 

[silent_guy]

I cannot imagine HBM being remotely price competitive compared to GDDR5. It has absolutely no business being part of a cost oriented APU solution if even GDDR5 is considered too much. Maybe we'll see HBM paired with an APU in 2 or 3 years. Maybe...

 

[Alexko]

I cannot imagine HBM being remotely price competitive compared to GDDR5. It has absolutely no business being part of a cost oriented APU solution if even GDDR5 is considered too much. Maybe we'll see HBM paired with an APU in 2 or 3 years. Maybe...

It was never entirely clear whether GDDR5 was deemed unsuitable for APUs solely because of cost concerns, or because of its supposed high latency. But I don't know how HBM's latency compares to DDR3/4 either.

 

[Kaotik]

— There will be desktop CPUs with Zen cores, but apparently APUs are still based on Excavator; at least AMD doesn't mention Zen for them—pretty disappointing! Desktop chips will be on AM4, while everything else will be on FP4;

I understood the orange coloring in said roadmap to mean Zen-cores for all around, including APUs

edit:
Just mentioned: Zen scales from high end CPUs to APU's to low power APUs

 

[silent_guy]

It was never entirely clear whether GDDR5 was deemed unsuitable for APUs solely because of cost concerns, or because of its supposed high latency. But I don't know how HBM's latency compares to DDR3/4 either.

I don't think the GDDR5 latency is longer than DDR3 in wall clock time. It's just longer in the number of cycles due to much higher clock.

At least that's what I remember when I last put the 2 data sheets next to each other to settle it in my mind once and for all. But maybe I was wrong back then...

 

[Alexko]

I understood the orange coloring in said roadmap to mean Zen-cores for all around, including APUs

edit:
Just mentioned: Zen scales from high end CPUs to APU's to low power APUs

Was that said specifically in the context of the 2016 roadmap?

 

[Kaotik]

Was that said specifically in the context of the 2016 roadmap?

No, they didn't specify 2016 roadmap, it was in the Q&A regarding AMD's cores since they now have "highend & lowpower architectures" but they only talked about Zen for future, AMD's answer was that Zen scales from top to bottom (and then there's K12 ARM)

 

[Alexko]

No, they didn't specify 2016 roadmap, it was in the Q&A regarding AMD's cores since they now have "highend & lowpower architectures" but they only talked about Zen for future, AMD's answer was that Zen scales from top to bottom (and then there's K12 ARM)

It's pretty obvious that any CPU core can be put into an APU, but it does not seem to be on the menu for 2016. That's a pity, because if Zen is as good as AMD seems to think, it could have made a huge financial difference.

Still, an 8-core Zen CPU could be pretty great for enthusiasts, assuming a reasonable price.

 

[Kaotik]

It's pretty obvious that any CPU core can be put into an APU, but it does not seem to be on the menu for 2016. That's a pity, because if Zen is as good as AMD seems to think, it could have made a huge financial difference.

Still, an 8-core Zen CPU could be pretty great for enthusiasts, assuming a reasonable price.

I wouldn't say "it's a pity" until it's confirmed one way or the other, I really doubt they're planning to stretch Excavator through 2016 which would leave Zen as only alternative. I regret missing part of the show, since even if they didn't mention cores for APUs, they might have mentioned process, if the 2016 APUs are 14nm they're Zen for sure

 

[Alexko]

I wouldn't say "it's a pity" until it's confirmed one way or the other, I really doubt they're planning to stretch Excavator through 2016 which would leave Zen as only alternative. I regret missing part of the show, since even if they didn't mention cores for APUs, they might have mentioned process, if the 2016 APUs are 14nm they're Zen for sure

They specifically mention Zen for CPUs in two distinct slides that also talk about APUs, but don't talk about Zen for those. It's not confirmed, but I'd say it's clear enough. And I don't see why 14nm should imply Zen.

 

[Kaotik]

They specifically mention Zen for CPUs in two distinct slides that also talk about APUs, but don't talk about Zen for those. It's not confirmed, but I'd say it's clear enough. And I don't see why 14nm should imply Zen.

Would they really still invest in BD-family to shrink it down to 14nm?

 

[Ryan Smith]

Would they really still invest in BD-family to shrink it down to 14nm?

FWIW, AMD has only ever mentioned FinFET CPUs/APUs within the context of Zen.

And keep in mind that AMD is trying not to Osborne Carrizo here.

 

[3dilettante]

The economics of the new node is a bit of an unknown. The likely introduction of Zen is in a segment that will probably pay more to justify the process switch, and 28nm is really being highlighted as a long-lived node in terms of cost-effectiveness.
I suppose in theory a shrunken Carrizo at around half the die size has more slack to compensate for a pricier process, with the caveat that it only works if AMD sells twice as many of its product at the same price. The data points supporting such an assumption for AMD are sparse.

 

[Entropy]

I cannot imagine HBM being remotely price competitive compared to GDDR5. It has absolutely no business being part of a cost oriented APU solution if even GDDR5 is considered too much. Maybe we'll see HBM paired with an APU in 2 or 3 years. Maybe...

No, HBM would be a part of a performance oriented APU solution first. But cost wouldn't necessarily be so bad if you ditched upgradeable memory, i.e. didn't have to drive DDR I/O or have memory sockets or traces on the motherboard and so on. I think this would be perfectly acceptable for most consumers. While DDR4 helps a bit, it won't increase graphics performance much over DDR3. It simply isn't good enough beyond minimal needs. There is no way AMD can leverage their graphics expertise in x86 space while being hobbled by the memory subsystem. They did have plans for HBM beyond GPUs, but - when? For what?
I'm a bit disappointed they don't go for this, but I guess they have checked interest with the major players. No point in producing a product that won't be bought by the IHVs.

 

[Deleted member 13524]

M300 GPUs are already in AMD's page, and it's even more boring than I imagined:

http://www.amd.com/en-us/products/graphics/notebook/r9-m200

M375 is a 10CU Cape Verde using DDR3 128bit memory.
M360 is a 6CU Oland with DDR3 64bit (15GB/s)
M330 is a 5CU Oland with DDR3 64bit

I imagine these are only useful to pair with Carrizo for dual-GPU and little else..

EDIT: M360 is also 64bit like kalelovil mentioned...

 

[kalelovil]

M300 GPUs are already in AMD's page, and it's even more boring than I imagined:

http://www.amd.com/en-us/products/graphics/notebook/r9-m200

M375 is a 10CU Cape Verde using DDR3 128bit memory.
M360 is a 6CU Oland with DDR3 128bit.
M330 is a 5CU Oland with DDR3 64bit (15GB/s)

I imagine these are only useful to pair with Carrizo for dual-GPU and little else..

R7 M360 has a 64bit DDR3 interface as well.
AMD are roughly halving memory bandwidth for the R7 and R9 compared to their M200 series predecessors, which will take a heavy toll on performance.

Cape Verde with DDR3 in the R9 series is simply pathetic. It destroys any sense of performance the R9 series branding used to infer. They are relegated to competing with the Geforce 840m/940m and below.

 

[Silent_Buddha]

No, HBM would be a part of a performance oriented APU solution first. But cost wouldn't necessarily be so bad if you ditched upgradeable memory, i.e. didn't have to drive DDR I/O or have memory sockets or traces on the motherboard and so on. I think this would be perfectly acceptable for most consumers. While DDR4 helps a bit, it won't increase graphics performance much over DDR3. It simply isn't good enough beyond minimal needs. There is no way AMD can leverage their graphics expertise in x86 space while being hobbled by the memory subsystem. They did have plans for HBM beyond GPUs, but - when? For what?
I'm a bit disappointed they don't go for this, but I guess they have checked interest with the major players. No point in producing a product that won't be bought by the IHVs.

Apparently you may not be disappointed for too long...possibly.

http://www.anandtech.com/show/9235/amd-to-launch-new-desktop-gpu-this-quarter-q215-with-hbm

Finally, while talking about HBM on GPUs, AMD is also strongly hinting that they intend to bring HBM to other products as well. Given their product portfolio, we consider this to be a pretty transparent hint that the company wants to build HBM-equipped APUs. AMD’s APUs have traditionally struggled to reach peak performance due to their lack of memory bandwidth – 128-bit DDR3 only goes so far – so HBM would be a natural extension to APUs.

If AMD are strongly hinting that it's bringing HBM to other products, that can really only mean APUs, IMO. The question then becomes what market segment will they target first with it? Gaming PC? Console? HPC?

Console would be an obvious win. But the only console maker that is potentially making a new console would be Nintendo. And they haven't pushed the limits on technology in home consoles in a while, handhelds are another matter. Still, if Nintendo went for it, that would be quite interesting.

Gaming PCs would be a fair bit riskier, although potentially much higher rewards. Gaming laptops would also potentially benefit immensely.

HPC is fairly obvious. Although there, it'd be more like another level of cache as memory pools tend to be much larger there.

Regards,
SB

 

[aaronspink]

I don't think the GDDR5 latency is longer than DDR3 in wall clock time. It's just longer in the number of cycles due to much higher clock.

At least that's what I remember when I last put the 2 data sheets next to each other to settle it in my mind once and for all. But maybe I was wrong back then...

Main difference is optimization points for rank width. GDDR5 is optimized around x16/x32 where as DDR3 is optimized around 64/128. Is GDDR5 still at BL=8 or did it move to BL=16?

Actual DRAM cells/arrays themselves should be virtually unchanged between DDR3/4, GDDR5, HMC, HBM, etc. And the arrays are what give you the basic PRE-RAS-CAS timings.

 

[silent_guy]

I think back then GDDR5 was BL8. Do you think it changed with higher speeds?