Speculation: GPU Performance Comparisons of 2020 *Spawn*

[yuri]

I mean 2 x 5700XT performance is perfectly reasonable to expect without overhyping anything. That's 33% faster than 2080Ti. I mean they even call the damn thing Navi2x. How much more obvious can it get?

Yes, this was obvious since the "Big Navi" surfaced. What is not clear is how they managed the 2*225W TDP, right?

 

[Leoneazzurro5]

AMD claimed 50% gain in performance per Watt in the passage from RDNA1 to RDNA2. If true, this may be done by architerctural improvements (bottleneck resolution, better IPC, improved power gating), better production process allowing better clock speeds and/or lower power consumption: so again, if claims are true for achieving 2x 5700XT performance they won't need 2x225W but 300W.

 

[Krteq]

No.

There's also patches for it with GDDR6.
Paranoid, survive, yadda, yadda, yadda.

Can you please link that commit with GDDR6 interface mentioned? All I can find is this one for Sienna and it clearly states HBM interface

Sienna - UMC 8.7: 2048-bit HBM2

UMC

+/* HBM  Memory Channel Width */
+#define UMC_V8_7_HBM_MEMORY_CHANNEL_WIDTH 128
+/* number of umc channel instance with memory map register access */
+#define UMC_V8_7_CHANNEL_INSTANCE_NUM 2
+/* number of umc instance with memory map register access */
+#define UMC_V8_7_UMC_INSTANCE_NUM 8
+/* total channel instances in one umc block */
+#define UMC_V8_7_TOTAL_CHANNEL_NUM (UMC_V8_7_CHANNEL_INSTANCE_NUM * UMC_V8_7_UMC_INSTANCE_NUM)
+/* UMC regiser per channel offset */
+#define UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA    0x400

GMC

+static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
+{
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
+ adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
+ adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;
+ adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;
+ adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];
+ adev->umc.funcs = &umc_v8_7_funcs;
+ break;
+ default:
+ break;
+ }
+}

Arcturus - for reference - UMC 6.1: 4096-bit HBM2

/* HBM  Memory Channel Width */
#define UMC_V6_1_HBM_MEMORY_CHANNEL_WIDTH    128
/* number of umc channel instance with memory map register access */
#define UMC_V6_1_CHANNEL_INSTANCE_NUM        4
/* number of umc instance with memory map register access */
#define UMC_V6_1_UMC_INSTANCE_NUM        8
/* total channel instances in one umc block */
#define UMC_V6_1_TOTAL_CHANNEL_NUM    (UMC_V6_1_CHANNEL_INSTANCE_NUM * UMC_V6_1_UMC_INSTANCE_NUM)
/* UMC regiser per channel offset */
#define UMC_V6_1_PER_CHANNEL_OFFSET_VG20    0x800
#define UMC_V6_1_PER_CHANNEL_OFFSET_ARCT    0x400

https://lists.freedesktop.org/archives/amd-gfx/attachments/20200727/dfe69333/attachment-0001.obj
https://lists.freedesktop.org/archives/amd-gfx/attachments/20200727/5df202da/attachment.obj

 

[no-X]

Max throughput.

Thanks for the reply. Does maximum theoretical throughput of a rasterizer / RBE in a console APU tell anything about rasterizer / RBE efficiency of a desktop GPU?

 

[CarstenS]

Thanks for the reply. Does maximum theoretical throughput of a rasterizer / RBE in a console APU tell anything about rasterizer / RBE efficiency of a desktop GPU?

No, it's one datapoint among many.

 

[Konan65]

AMD claimed 50% gain in performance per Watt in the passage from RDNA1 to RDNA2. If true, this may be done by architerctural improvements (bottleneck resolution, better IPC, improved power gating), better production process allowing better clock speeds and/or lower power consumption: so again, if claims are true for achieving 2x 5700XT performance they won't need 2x225W but 300W.

What is the math thinking on that? Wouldn't it be higher that 300W?

 

[DegustatoR]

What is the math thinking on that? Wouldn't it be higher that 300W?

5700XT is 225W.
Which means that you should get 5700XT performance on RDNA2 in 150W if it will have 50% better perf/watt.
So double 5700XT on RDNA2 will net you 300W.

 

[Bondrewd]

So double 5700XT on RDNA2 will net you 300W.

ALUs, yes, other stuff, not really.

 

[Leoneazzurro5]

It was a gross "calculation" btw. Not accounting the fact that 225W is the board power, not the ASIC.

 

[DegustatoR]

Well, yeah, it will scale differently for TBP because the chip won't get 50% less TDP and the memory will likely be faster and eat more than on 5700XT but the rough ballpark will be close.

 

[Bondrewd]

but the rough ballpark will be close.

not even remotely

 

[trinibwoy]

not even remotely

Not remotely 300w or not remotely twice as fast as 5700xt? Maybe neither?

 

[Bondrewd]

Maybe neither?

Kinda neither in the most hilarious way imagineable.
Get your popcorn reserves going.

 

[Konan65]

Kinda neither in the most hilarious way imagineable.
Get your popcorn reserves going.

@Bondrewd
Kinda like these targets heard

Navi 23 - 150W = 2080S +5-10% perf.
Navi 22 - 225W = 2080Ti ~+15% perf.
Navi 21 - 275W = 2080Ti. ~+40% perf.

 

[Nebuchadnezzar]

The very earliest rumours last year said 2.7x GTX1080 in regards to their internal targets for AMD so sounds about right.

 

[CarstenS]

@Bondrewd
Kinda like these targets heard

Navi 23 - 150W = 2080S +5-10% perf.
Navi 22 - 225W = 2080Ti ~+15% perf.
Navi 21 - 275W = 2080Ti. ~+40% perf.

Frankly, 2+ years later and on more-than-a-full-node advantage, I would not expect less.

 

[pTmdfx]

Can you please link that commit with GDDR6 interface mentioned? All I can find is this one for Sienna and it clearly states HBM interface

You don't need to get everything parameters for bringing up a chip. 8 UMCs * 2 channels works fine for 512-bit GDDR6 too.

 

[pjbliverpool]

@Bondrewd
Kinda like these targets heard

Navi 23 - 150W = 2080S +5-10% perf.
Navi 22 - 225W = 2080Ti ~+15% perf.
Navi 21 - 275W = 2080Ti. ~+40% perf.

I hope this is true for competitions sake. I was pretty much set on NV for my next card thanks to DLSS, but if DLSS remains restricted in it's implementation and the price is right on Navi 22 then I could certainly be tempted at that performance level.

 

[Bondrewd]

I hope this is true for competitions sake

AMD wants to win, especially the laptops where their leverage now is huge.

I was pretty much set on NV for my next card thanks to DLSS, but if DLSS remains restricted in it's implementation and the price is right on Navi 22 then I could certainly be tempted at that performance level.

I wanna see vendor-agnostic take on ML upscaling because I hate IHV-specific bullshit all the same.
DML, hurrah.

 

[w0lfram]

I hope this is true for competitions sake. I was pretty much set on NV for my next card thanks to DLSS, but if DLSS remains restricted in it's implementation and the price is right on Navi 22 then I could certainly be tempted at that performance level.

I would think that directML would get wider adoption than brand specific DLSS. NVidia cards will still have to support directML regardless, so I think Game Devs would spend their efforts there.

Considering it also pays off with the Series X games and development.