Well... we do not know if Cell is receiving the same kind of automated design that was behind the POWER4.
I do not think we should assume this...
After all the reason behind that choice of IBM was to allow POWER4 and POWER4+ to beat Itanium 2 on the market ( McKinley and Madison ) and they managed it and the CPU still performs quite well...
Cell might be a different case...
As far as manufacturing processes are concerned Toshiba and SCE are going to be ready next year ( mid 2004 ) to mass manufacture 65 nm chips on 300 mm wafers.
This is the process that is going to be used for Sony's Cell chips...
- LARGE clock rate advantage.
- Enhanced ALUs and more of them
- Enhanced FP performance via SSEx
- More instructions per clock from the trace cache.
- Large and faster cache heirarcy
- Enhanced Hyper-Threading
- Possible Multi-core.
- Additionally light workload.
Faster ALUs, yes I can give it to them due to clock-speed advantage and very good branch prediction...
More ALUs than Cell ? The Broadband Engine chip is expected to have something like 128 Integer Units and 128 FP Units.
SSE delivering enhanced performance... well they could start adding more than 8 XMM registers and maybe add FP MADD instructions and allow non destructive instructions ( ex: R1 = R2 * R4 + R5 instead of op1 = op 1 <arithm> op2... ).
Enhanced Hyper-Threading... that is nice ( trust me, I do believe it is a ncie addition as this way the IPC is effectively increased, better efficientcy is achieved ), but the Cell chip will use Multi-Threading as well...
Uhm... I thought you were talking about the enhancements of a 2005 IA-32 chip ( based of the Netburst architeture ) over the current Northwood...
Sorry I misunderstood it as a "vs Cell" kind of comparison...