I'm transcripting these quotes from PS3Insider's Forum cause I believe this stuff is very interesting
All these quotes come from the same guy (his name is cpiasminc) from several posts:
ciao,
Marco
All these quotes come from the same guy (his name is cpiasminc) from several posts:
(note: he went to SCEA offices a couple of times..first time he saw a test board clocked at 1.15 Ghz. When he went over the second time he was told about the 9 gigaflop/s per APU figure)I did go visit another SCEA office yesterday, and one of the guys said that the samples they had (again 1.15 GHz, I assume -- they didn't say) achieved a peak of around 9 GFLOPS to each APU. Now if I assume that it is 1.15 GHz, that means that eiher the APU is 256-bit (and can therefore do 8 32-bit FLOPS per cycle), or it is 128-bit and is a wide issue multi-pipe APU and can issue up 2 SIMD instructions per cycle (which would be better). Unless it supports 16-bit floats as well, which I don't know why they would. Anyway, that would yield 8 FLOPS per cycle and therefore 8 * 1.15 GHz = 9.2 GFLOPS. Sounds about right. Unless this office has double the clock of the mock-ups I saw before
...Well, the engineering samples I saw were running pretty darn fast. They were only 1.15 GHz, but the guy did say they were pretty old (consider the fact that these parts happened to ship to California...) At the 1.15 GHz level, the wattage was only around 20 W running Soul Reaver inside the still buggy PS2 emulator. However, the actual power consumption will go up as clock speed rises, and the practical consumption will go up as your code better utilizes the processing facilities.
....Everything was pretty encouraging except for sound. None of the mock-ups had sound yet. The guy said that they Sony have to evaluate some costs in order to make any decision about the final audio arrangement. I did have to sign an NDA so I'm not allowed to say much, and they were also kind of vague about it. I got the impression that they're not even sure where to put it in the pecking order. Considering that cost was brought up, I'd have to wager that there may not be a third Cell-like chip that uses DSP-based APUs for sound. It may just end up with an off-the-shelf audio controller.
Developers only have cycle-counting emulators. So their tests run at around 0.2 fps or so, but there's a little clock-cycle estimator in the corner. And apparently since the scheduling/distribution logic isn't so well emulated, the clock cycle estimator is said to be correct within 5-10%, which is basically really bad.
I still have doubts about the schedule. They gave me no guesses regarding how on-track they are and they have no info about how far things are in Japan.
BTW, there was news a long time ago of CELL prototypes running at 200-800 MHz, and those were of all sizes ranging from 4 APUs to 128 APUs
ciao,
Marco