So do you think the Nintendo Revolution will use Z-RAM?

[Brimstone]

Whats intresting is that Innovative Silicon has their Z-RAM technology which is more advanced than Mosys eDRAM that the Gamecube uses. The Fab giant TSMC also has their eDRAM process based off of Mosys 1t-SRAM technology. So if the Xenon GPU has eDRAM, it would probably be based off of the Mosys technology.

Now Mark-Eric Jones, the CEO of Innovative Silicon, is a former employee of Mosys, where he was vice president and general manager of Intellectual Property. He surely has contacts at ATI, NEC, and Nintendo.

Also the possibility exists for the revolutions dram based off of this technology.

As the planar technology, at 4F2, has half the bit cell size of conventional DRAM the technology would also be suitable for displacing DRAM technology in standard products.

"Yes, it could do commodity parts. But, mainly for business reasons, we're not going there, initially. There's a high barrier to entry in commodity parts."

Source

The most advanced Micron has right now is 6F, so it would better than that density wise. Compared to 8F, 6F is about 20% smaller.

Source

Now if Nintendo got a Rambus XDR license combined with the Innovative Silicon Z-RAM architechture for the Revolutions DRAM that would be intresting. Since Nintendo used Mosys technology for DRAM as well as eDRAM, I don't think this is too far fetched. Matsushita, an ally of Nintendo, has intrest in Rambus XDR for consumer devices, so jointly using the same DRAM could help maintain high volume to keep costs as low as possible.

 

[Megadrive1988]

what are the features & advantages of Z-RAM?

 

[Li Mu Bai]

what are the features & advantages of Z-RAM?

Everything regarding Z-RAM right here for ya Md:

Jan. 24, 2005--Innovative Silicon Inc. (ISi) has launched its Z-RAM(TM) embedded memory technology for SoCs which doubles memory density when compared to existing embedded DRAM solutions. The Z-RAM (Zero Capacitor
RAM) technology harnesses the Floating Body (FB) effect that occurs in Silicon-On-Insulator (SOI) devices, resulting in a cell structure that is based on a single transistor alone, rather than the combination of a transistor and a capacitor. Z-RAM memory designs have been taped out at 90nm and the technology is scalable to 22nm design rules. More, unlike other high density memory technologies, Z-RAM technology requires no extra mask steps, or exotic materials.

In SOI devices, the Floating Body or Body Charging effect which results in a charge developing in the FET device body has generally been considered as a parasitic effect. ISi has developed a mechanism to control and enhance this FB charge, which can then be used to store "1" or "0" binary states. Information is read by comparing the current in a selected cell to a reference, using a current sense amplifier.

SOI is emerging as the process technology of choice for high performance SoCs and Microprocessors, with leading processor and games companies already switching away from bulk CMOS to take advantage of the increased performance and reduction in power that SOI delivers. Explains ISi CEO, Mark-Eric Jones: "Embedded memory occupies at least 70 per cent of the die area of today's complex SoCs. The combination of our Z-RAM memory - which requires less than half the die area required for traditional embedded DRAM, without the additional process steps required to embed traditional DRAM - and existing SOI processing, which additionally offers large performance and power benefits, means that not only are Z-RAM SoCs higher performance and lower power, they are also much cheaper than SoCs based on bulk CMOS wafers."

He continues: "By reversing the traditional economics and making SOI wafers a lower cost solution than bulk silicon for most SoCs and microprocessors, we expect our Z-RAM memory technology to accelerate the anticipated industry switch from bulk silicon to SOI. As a result designers of cost-sensitive products will also be able to take advantage of the increased performance and lower power consumption of SOI."

Finally, Z-RAM technology does not require designers to compromise on speed or power: read and write operations in under 3nS have already been demonstrated on silicon; while ISi's low power Z-RAM option promises significant power savings compared to traditional embedded DRAM.

Concludes Jones: "Since Z-RAM technology uses a single transistor and no capacitor in the bitcell it is much more scalable than alternative DRAM and SRAM technologies. We have already demonstrated a Z-RAM memory cell using FinFET technology and expect Z-RAM to easily meet the high density embedded memory requirements of chip designers for the next 15 years.

Again, everything based upon the one transistor design philosophy. It would indeed be impressive if Nintendo incorporated this into the Revolution's architecture. And given Nintendo's inclination to work with the same technology suppliers, (given Mark Jones' former standing with Mo-SyS & Nintendo connections he obviously made there) it is at least a possibility as Brimstone stated.

 

[Li Mu Bai]

Perhaps even a fairly good possibility?

"We are going in a different direction than Sony. We believe that other companies are already investing in state-of-the-art semiconductor development, says Iwata. "Nintendo is not actually trying to create a state-of-the-art technology that is not known to the world. We are reviewing technologies that are in the early stages of development [by other companies]. Nintendo should be able to find the optimal solution to make the best possible hardware by cooperating with several partners."

Iwata: April 11, 2004

http://www.gamespy.com/articles/505/505234p4.html

ISi was well underway with their Z-RAM R&D at that point. I suspect the Revolution's specs would have to be finalized by mid-year at the latest. (barring speed & amount adjustments made to the central processor & ram allocations) We'll know for sure in May.

 

[Panajev2001a]

what are the features & advantages of Z-RAM?

Everything regarding Z-RAM right here for ya Md:

Jan. 24, 2005--Innovative Silicon Inc. (ISi) has launched its Z-RAM(TM) embedded memory technology for SoCs which doubles memory density when compared to existing embedded DRAM solutions. The Z-RAM (Zero Capacitor
RAM) technology harnesses the Floating Body (FB) effect that occurs in Silicon-On-Insulator (SOI) devices, resulting in a cell structure that is based on a single transistor alone, rather than the combination of a transistor and a capacitor. Z-RAM memory designs have been taped out at 90nm and the technology is scalable to 22nm design rules. More, unlike other high density memory technologies, Z-RAM technology requires no extra mask steps, or exotic materials.

In SOI devices, the Floating Body or Body Charging effect which results in a charge developing in the FET device body has generally been considered as a parasitic effect. ISi has developed a mechanism to control and enhance this FB charge, which can then be used to store "1" or "0" binary states. Information is read by comparing the current in a selected cell to a reference, using a current sense amplifier.

SOI is emerging as the process technology of choice for high performance SoCs and Microprocessors, with leading processor and games companies already switching away from bulk CMOS to take advantage of the increased performance and reduction in power that SOI delivers. Explains ISi CEO, Mark-Eric Jones: "Embedded memory occupies at least 70 per cent of the die area of today's complex SoCs. The combination of our Z-RAM memory - which requires less than half the die area required for traditional embedded DRAM, without the additional process steps required to embed traditional DRAM - and existing SOI processing, which additionally offers large performance and power benefits, means that not only are Z-RAM SoCs higher performance and lower power, they are also much cheaper than SoCs based on bulk CMOS wafers."

He continues: "By reversing the traditional economics and making SOI wafers a lower cost solution than bulk silicon for most SoCs and microprocessors, we expect our Z-RAM memory technology to accelerate the anticipated industry switch from bulk silicon to SOI. As a result designers of cost-sensitive products will also be able to take advantage of the increased performance and lower power consumption of SOI."

Finally, Z-RAM technology does not require designers to compromise on speed or power: read and write operations in under 3nS have already been demonstrated on silicon; while ISi's low power Z-RAM option promises significant power savings compared to traditional embedded DRAM.

Concludes Jones: "Since Z-RAM technology uses a single transistor and no capacitor in the bitcell it is much more scalable than alternative DRAM and SRAM technologies. We have already demonstrated a Z-RAM memory cell using FinFET technology and expect Z-RAM to easily meet the high density embedded memory requirements of chip designers for the next 15 years.

Again, everything based upon the one transistor design philosophy. It would indeed be impressive if Nintendo incorporated this into the Revolution's architecture. And given Nintendo's inclination to work with the same technology suppliers, (given Mark Jones' former standing with Mo-SyS & Nintendo connections he obviously made there) it is at least a possibility as Brimstone stated.

Interesting, this is the same kind of technology Toshiba is working on with SCE:

http://www.toshiba.co.jp/about/press/2003_06/pr1301.htm

(Toshiba expects it to be available on their 45 nm manufacturing process although it is not excluded that if the GPU has e-DRAM and it is done on an SOI process at 65 nm then they might use this technology earlier... still it is there for a die shrink later on if they do not use it at launch)

 

[PC-Engine]

If it's the same then wouldn't Toshiba be infringing SI's patent?

 

[Panajev2001a]

If it's the same then wouldn't Toshiba be infringing SI's patent?

I did not say it is exactly the same and using the physical property of SOI to take the capacitor away can be relaized in different ways and Toshiba might have tarted earlier than these guys pr they might have alreayd a cross-license agreement or there is prior art for both.

 

[Brimstone]

what are the features & advantages of Z-RAM?

A GPU with Z-RAM compared to one with MoSyS 1T-SRAM, should clock higher because it works well with a SOI. Also since it doesn't use a capacitor, it's very compact, so more ram can be embedded in the same amount of area. The Z-RAM technology combined with Intrinsity Fast-14, could make the Revolutions ATI GPU very impressive. I assume NEC would FAB it at the .65 nm node.

 

[Li Mu Bai]

Verified Operability

Toshiba's experimental 96Kbit cell array achieved successful operation in all bits, a 36-nanosecond access time, 30-nanosecond data switching time, and 500-millisecond data retention time (at 85 degrees C). The results demonstrate that the new FBC technology can be applied to system LSI integrating DRAM cells with megabit or greater memory capacity.

Very similar Pana, though not quite as fast as Z-RAM's read & write sub 3ns capability. Still very impressive though.

 

[phat]

Verified Operability

Toshiba's experimental 96Kbit cell array achieved successful operation in all bits, a 36-nanosecond access time, 30-nanosecond data switching time, and 500-millisecond data retention time (at 85 degrees C). The results demonstrate that the new FBC technology can be applied to system LSI integrating DRAM cells with megabit or greater memory capacity.

Very similar Pana, though not quite as fast as Z-RAM's sub 3ns capability. Still very impressive though.

I think Innovative only has functional single bit prototypes, not cell arrays. So, 3ns access time on a single bit is not that impressive compared to 36ns for a fully addressed 96kbit cell array.

Phat

 

[Li Mu Bai]

I think Innovative only has functional single bit prototypes, not cell arrays. So, 3ns access time on a single bit is not that impressive compared to 36ns for a fully addressed 96kbit cell array.

Phat

This is true Phat, as I read further upon the topic that sub 3ns is simply what was possible utilizing a single bit access by ISi. (specs. provided by ISi specifically for the press release meant to demonstrate the impressive speed of Z-RAM undoubtedly) Given that their tech. premises are indeed quite similar, (capacitor free) do you truly expect a considerable vs. a negligible difference when addressing a cell array? Also coupled with Fast-14's technology? Especially if Nintendo does not wish to go the parallel processing route. (which they don't imo due to the added programming complexity, esp. from their design philosophy viewpoint) IIRC those two early Revolution design specs showed two central processor possibilities, one dual & an alternative single core.

The three primary benefits of Fast14 Technology are:

Higher Performance
CMOS process improvements no longer yield dramatic performance increases. Fast14 Technology has achieved multi-GHz performance in processes ranging from 180nm to 130nm. Performance of 400 MHz to 4 GHz is achievable with Fast14 Technology at 90nm and 65nm without requiring exotic processing techniques.

Lower Die Cost
As process improvements offer diminishing returns, entire classes of products have resorted to parallel processing to stay competitive. Fast14 Technology reduces area by replacing numerous parallel processing elements with single elements operating at much higher frequencies.

Lower Power
Beyond 300 MHz, traditional design methods rapidly lose power efficiency due to higher voltages and larger transistors. Each CMOS process generation compounds leakage problems by an order of magnitude. Fast14 Technology reduces leakage through transistor efficiency and lower voltage while enabling multi-GHz performance.

ISi taped out its first 90nm megabit Z-RAM memory designs in 2004. Its technology is scalable down to 22nm design rules. (using FinFET?) And no, I don't expect it to to go that low during a console's lifecycle, as it would be I'm sure cost prohibitive. Still worthy of noting nonetheless. Fast-14 & ATi also announced a technology licensing agreement on Feb. 5th of 2004 as well. The more I research these developments, the more I am convinced that the Revolution will have part, if not all of these incorporated into its architecture in '06. An almost natural progression, or evolution of what the GC is architecturally in this generation. Even looking at such variables as price, efficiency, power consumption, ram, design simplicity, etc. Essentially advancing & further refining the GC's design (& Nintendo's own dev. philosophy for EAD & its other in-house studios) with next-gen. technologies.

 

[pc999]

If not Nitendo at least MS, once that they want to cut costs

 

[Li Mu Bai]

If not Nitendo at least MS, once that they want to cut costs

I thought Xenon's ram type had been identified? Nintendo is always looking towards the future & the potential for cost efficiency. That is why I see this route as providing the best cost-to-performance ratio for the Revolution. I guess forummites here aren't interested in speculating on Nintendo's next platform? Since it's not CELL or Xenon.

 

[one]

If not Nitendo at least MS, once that they want to cut costs

I thought Xenon's ram type had been identified? Nintendo is always looking towards the future & the potential for cost efficiency. That is why I see this route as providing the best cost-to-performance ratio for the Revolution. I guess forummites here aren't interested in speculating on Nintendo's next platform? Since it's not CELL or Xenon.

Is Z-RAM cost efficient? The IP licensing cost for it won't be disclosed so we won't know, though.

 

[Li Mu Bai]

Is Z-RAM cost efficient? The IP licensing cost for it won't be disclosed so we won't know, though.

He continues: "By reversing the traditional economics and making SOI wafers a lower cost solution than bulk silicon for most SoCs and microprocessors, we expect our Z-RAM memory technology to accelerate the anticipated industry switch from bulk silicon to SOI. As a result designers of cost-sensitive products will also be able to take advantage of the increased performance and lower power consumption of SOI."

In comparison to the current e-DRAM solutions & their cost implementation, he's saying that it is. By a seemingly significant margin as well.

 

[phat]

This is true Phat, as I read further upon the topic that sub 3ns is simply what was possible utilizing a single bit access by ISi. (specs. provided by ISi specifically for the press release meant to demonstrate the impressive speed of Z-RAM undoubtedly) Given that their tech. premises are indeed quite similar, (capacitor free) do you truly expect a considerable vs. a negligible difference when addressing a cell array?

Z-RAM has faster cell access time than DRAM, but it can't be faster than SRAM, so I'd expect a Z-RAM memory array to have access times between those of SRAM and DRAM memory arrays. SRAM memory has access times between 20-30ns, and DRAM between 60-120ns, so Z-RAM should be between 30-60ns. Toshiba's technology is at 36ns, so Z-RAM should be comparable.

 

[j^aws]

....
I guess forummites here aren't interested in speculating on Nintendo's next platform? Since it's not CELL or Xenon.

I'm pretty sure this Z-RAM has a good chance of making it into a late 2005/2006 console as it works with 90nm, is fast and area efficient...all good ingredients!

Also, I wouldn't say not interested in Ninty's next console. I've started several topics and so have others but I think it's due to the lack of some juicy material to sink your teeth into and use as a reference. Xenon has the leaked specs and diagram and CELL has a miriad of patents but no similar material for Rev.

On a side note, I do believe IBM is using the next three consoles as an R&D testbed for a range of CPU tech and design philosophies and why not, as the experience gained would only benefit them.

Maybe we'll see three fairly distinct designs, i.e. we'll see the extremely parallel, multi-core CELL; the Xenon CPU, a more conventional multi-core design; and I believe Revolutions CPU will be single core (max. dual) but highly Superscaler in design. Maybe an 8-way superscaler design?

I'm pretty sure Ninty will have eDRAM on the GPU and obviously fast system RAM but I don't know if they'll ditch the large pool of slower/cheaper Auxilliary/Audio A-RAM but I'm sure, overall, they'll have a very efficient, cost-effective console design!

 

[Iron Tiger]

If it's the same then wouldn't Toshiba be infringing SI's patent?

I did not say it is exactly the same and using the physical property of SOI to take the capacitor away can be relaized in different ways and Toshiba might have tarted earlier than these guys pr they might have alreayd a cross-license agreement or there is prior art for both.

You could have just referred him to your sig

Especially if Nintendo does not wish to go the parallel processing route. (which they don't imo due to the added programming complexity, esp. from their design philosophy viewpoint) IIRC those two early Revolution design specs showed two central processor possibilities, one dual & an alternative single core.

But then the DS has two processors which can be used for separate applications or to assist each other in one application. And if parallelism is the future, ALL developers are going to have to get used to it, just as they had to adapt to moving from 2D development to 3D. Nintendo's commitment to simplicity can still shine through in other ways.

Nintendo can surely appreciate the potential of more CPU power, as they've used the GC's CPU to aid the GPU in rendering in some games. A game like "Luigi's Mansion 2" could have AI and complex particle physics done on one CPU, with object physics on the other. Or one CPU can handle vertex functions and save buffered vertex data to do wavetraced sound, while the other handles AI, physics, etc.

And in keeping with their ideals, I doubt that they'd wish to use RAMBUS memory any time soon. They went back to "SRAM" in the GC because of the lower latency, which they prefer over higher bandwidth. That said, Z-RAM does seem like a perfect fit for them. What if they have dedicated embedded memory for each part now, instead of a pool of system memory?

 

[pc999]

If not Nitendo at least MS, once that they want to cut costs

I thought Xenon's ram type had been identified? Nintendo is always looking towards the future & the potential for cost efficiency. That is why I see this route as providing the best cost-to-performance ratio for the Revolution. I guess forummites here aren't interested in speculating on Nintendo's next platform? Since it's not CELL or Xenon.

Actually, for me at least seems like MS is trying to do the same, a cost-efficient console over time, at their own way.

 

[Brimstone]

And in keeping with their ideals, I doubt that they'd wish to use RAMBUS memory any time soon. They went back to "SRAM" in the GC because of the lower latency, which they prefer over higher bandwidth. That said, Z-RAM does seem like a perfect fit for them. What if they have dedicated embedded memory for each part now, instead of a pool of system memory?

Rambus XDR for signaling. I was speculating the Z-RAM for the DRAM combined with the XDR topology.

Who fabs the Gamecubes MoSys DRAM anyway?