Indeed it doesn't make sense.On every single instance (Kernel sources for Exynos, talks with some lead devs, Google's gerrit patches) points out that the CCI is powered off and inactive.
Of course it doesn't make much sense given some of the chip layouts we know of, even if just the ports are disabled: http://i.imgur.com/6wunhUQ.png
I looked at this code:
https://github.com/AndreiLux/Perseu...erseus/arch/arm/mach-exynos/bL_control.c#L400
Code:
static size_t bL_check_status(char *info)
{
...
len += sprintf(&info[len], " %d\n",
(readl(cci_base + 0x4000 + 1 * 0x1000) & 0x3)
== 3 ? 1 : 0);
...
len += sprintf(&info[len], " %d\n\n",
(readl(cci_base + 0x4000 + 0 * 0x1000) & 0x3)
== 3 ? 1 : 0);
}
If you look at the CCI TRM Register summary, you'll see that if the printed 2 bits are 0 it just means DVM and snoop requests are disabled from slave 3 and 4.
OTOH I perhaps missed the comments that explicitly state that the CCI is off in the kernel. Could you please point me to the proper file to look at?