RXXX Series Roadmap from AnandTech

[g__day]

If pipelines rather than being hardwired to ALUs, TMUs etc have access to a dynamically allocated pool of h/w resources - then the power of this rig must be a function of pipelines, low level shader units and the number of interconnects (buses) between each of these units.

Could the 1 vs 3 between R520 and R580 be the number of internal buses between the pipelines and the pooled resources that get dynamically allocated?

 

[Ailuros]

Have we yet reached a consensus on the X-X-X-X syntax, or are we still scratching around in the dark?

Xmas' input helped a bit speculating any further, but I think we're still scratching around in the dark.

First number makes sense to indicate ROP count on RV530, which should mean 4*600= 2400MPixels/s. Last number being most likely TMU count in the given case 8*600= 4800MTexels/s.

All my other attempts to try to calculate something with the "3" compared to the 16/1/1/1 in R520 turns into utter nonsense.

NV43 has also a few elements that were indicative of what was to come in G70 and it has coincidentally 4 ROPs too.

 

[Dave Baumann]

But how does that reconcile with the idea that RV530 is 12 pipes...?

 

[caboosemoose]

But how does that reconcile with the idea that RV530 is 12 pipes...?

Is that an idea that we need to reconcile?

 

[Jawed]

An alternative tack might be to ask why does this #-#-#-# notation exist?

Looking beyond R580 into R600, how might this notation be employed?

If we apply this notation to Xenos, then we might get:

ROPs - Shader Arrays - ALUs per array per ROP - TMUs per ROP

8-3-2-2

As a matter of interest I'm ignoring point-sampling (Xenos can also point-sample 16 textures), because I think point-sampling is actually done by the fragment shader ALUs directly from texture cache. Though I'm not too sure about this, as I don't know what ramifications it might have for dependent texturing (if successive orders of texture operations are all point-sampled an address is required and I don't know where the address is calculated in this case - ARGH).

Also implicit here is the idea that the TMU pool is shared by both the vertex and fragment shader pipelines.

Jawed

 

[caboosemoose]

An alternative tack might be to ask why does this #-#-#-# notation exist?

Jawed

Well, I'm not sure I'd read too much into it - it's not designed for public consumption. It might be a clever way of designating chip architecture that gives a good idea of overall 3D rendering capability. Or it might simply reflect some rather arbitrary internal classification scheme.

 

[Rys]

But how does that reconcile with the idea that RV530 is 12 pipes...?

It doesn't, because it's not.

 

[Dave Baumann]

The word pipes should be quoted (see my earlier post to Nick).

 

[Geo]

I would like to point out, IIRC, that Anandtech had R420 down as an eight extreme pipe part until very close to the time that part launched. They are an awfully long way from infallible - they tend to either be under NDA and therefore not say anything or spouting fairly crackpot third hand info. I also find the 1400MHz memory spec on a mid range card somewhat unlikely, given that NVIDIA have not been able to specify that on the 7800 GTX.

Have we yet reached a consensus on the X-X-X-X syntax, or are we still scratching around in the dark?

I dunno. I put a lot of stock in the fact that the Anand piece showed up almost immediately after Wavey's own piece on timing, confirming it and adding more detail. And Wavey has implicitly accepted the 12 pipes for RV530 in several posts above. So it sniffs to me very much like they are working from the same source, most likely an official roadmap document thrown over the transom by an AIB. That's my read.

 

[Unknown Soldier]

I got it.

The 3 vs the one means Embedded memory size.

The R520 has 1 meg and the R580 has 3.



please don't take me seriously.

US

 

[caboosemoose]

I dunno. I put a lot of stock in the fact that the Anand piece showed up almost immediately after Wavey's own piece on timing, confirming it and adding more detail. And Wavey has implicitly accepted the 12 pipes for RV530 in several posts above. So it sniffs to me very much like they are working from the same source, most likely an official roadmap document thrown over the transom by an AIB. That's my read.

Much in the piece may be accurate, but that doesnt mean it all is. I don't know what the truth is other than the original numbers over which we are all arguing the meaning, but I will be very surprised if RV350 turns out to be 12 pipes in the conventional sense.

 

[Jawed]

At the end of the Thread Handling section of the Xenos article:

http://www.beyond3d.com/articles/xenos/index.php?p=08#thread

we have:

The throughput of the system is such that ATI expect to be able to achieve two loops, two texture instructions and 6 ALU instructions per pixel, per cycle at Xenos's peak fill-rate.

Note, firstly, that this is expressed in terms of "per cycle peak fill-rate", i.e. per ROP per cycle. Also noteworthy is that this describes pixels - no mention of vertices.

I wonder if this would give rise to this notation:

ROPs - loops - ALUs - TMUs

8-2-6-2

Although, again, there's the sticky problem of counting filtering and point-sampling TMUs (the latter, arguably, is nothing more than a memory access rather than a texture operation).

Why does this statement make such a clear point about loops? Apart from anything else, I can't find anything in the article about Xenos that justifies this "2 loops per pixel" fact.

One would hope that an SM3 architecture would differ from an SM2 architecture in supporting dynamic loops. Is this Xenos hint about loops also a hint about ATI's SM3 architectures?

Are these four related facts, as per the Xenos article, the four elements of the #-#-#-# notation?

Jawed

 

[Geo]

http://69.93.88.162/forum/viewtopic.php?p=161396#161396

Ish. Don't see any "early September" in here. I'm not signing up for any of the performance speculation either. Yet. A 500mhz R520 spanking the GTX?

Edit: Oh, I guess the reviews part would be "early September". Which would also not follow Orton's statement to have reviews and availability in the same time frame in the June call. Tho they may have slid some more and now are faced with deciding which promise to break --launch "late summer" or same timeframe availability.

 

[wireframe]

But how does that reconcile with the idea that RV530 is 12 pipes...?

According to this 12 pipe RV530, is the G70 a 16 or 24 pipe architecture? (I am already getting confused at how the word pipeline is being used, even after thoroughly reading threads that "redefine pipelines"..or maybe that is why I am confused).

 

[caboosemoose]

According to this 12 pipe RV530, is the G70 a 16 or 24 pipe architecture? (I am already getting confused at how the word pipeline is being used, even after thoroughly reading threads that "redefine pipelines"..or maybe that is why I am confused).

Best to think of G70 as being 24 fragment / 6 quad and that Anandtech are suggesting RV530 is 12 fragment / 3 quad, I think.

 

[Rys]

Best to think of G70 as being 24 fragment / 6 quad and that Anandtech are suggesting RV530 is 12 fragment / 3 quad, I think.

Which is wrong

 

[caboosemoose]

Indeed, very probably, given that RV350's RPI (relative performance index) vs R520 is rated at 0.5x(+). By contrast, R580 is 1.5(+)...

 

[Rys]

We're hitting up against the language barrier again here, which is annoying me no end. What I'm saying is right in one respect (IMHO), what Dave is saying/hinting ( ) is right in another (IMHO again). It all depends on the definition of a pipe.

For me, it's something with only one path from input to output...

Which is how we're differing in what we're saying, which is essentially the same thing and that there's (seemingly I might add, I have no concrete info on this stuff, only the info in front of me which is what we all have, if you know where to look) extra internal parallelism to the fragment unit (of which there's only 4 in RV530).

The language for these things currently sucks big time (and so does the vague hinting, haha!)

 

[Dave Baumann]

Note that I'm not saying what constitutes a pipeline, I'm saying what is now commonly being referred to in terms of "pipes" elsewhere and then consider how that might relate to the two bits of information (1.) Anands article,2.) the stuff seen here)

 

[Sunday]

Just a couple of facts from mine testing:

Setup is: Athlon64FX 57 And BBA X850XT PE

Case one: GPU/MEM – 500/1000 MHz

3DMark03 - 13183
3DMark05 – 6108

Case two: GPU/MEM – 600/1200 MHz

3DMark03 – 15035
3DMark05 – 7166

Case three: Gigabyte 7800GTX (430/1200), same CPU:

3DMark03 - 16909
3Dmark05 - 7821

So, do the math wit the 700/1400 MHz in the case of R480, and spice it with jus a bit a guessing on R520 improvements and try figure out performances of the 16 pipe GPU! I think that with 16 pipe architecture R520 could easily bit up 7800GTX!

Also one more thing!

I’ve just tested ASUS 7800GTX TOP! This is a biffed up 7800GTX with Artic-alike cooling. By default it is clocked 495/1380 MHz! With Venice 3000+ (A64 - 1.8GHz/512k cache) I’m getting around 8200 3DMark05 points. With stock clocked 7800GTX that number is around 7.6K.

So, scenario, as I see it is: X900XT will hit around near 9K, and ‘vidia will answer it with 7800Ultra clocked, and cooled just like brand new Quadro, but with 1.4ns memory! Then, ATi will respond with R580 that has spec unknown to me.

In mine opinion, ATi was aware that will lose “back to school†season, and decided to work out strategy for holydays season. But ‘vidia is not naïve, and they are binning high quality G70 cores, preparing for strike with Ultra!