So the RV350 is either done on the general, high speed or mixed-signal product line. Question, are any of these choices in logic families indicative of lower yields?
Honestly, I'm not qualified to answer that.
EDIT: [meandering rant follows]
All things considered, I tend to believe ATI's design choices (choice of CAD-tools, design/implementation style) and 'risk management' are more important than the choice of logic families.
Every manufacturing process has an intrinsic 'defect-rate' (dust particles landing on wafer, impurities in the base layers, poorly formed metal, etc.) In broad terms, 'wafer defects' are generally imperfections intrinsic to the manufacturing process (because no one can build 100% clean-rooms.) As a fab-customer, you have NO control over the manufacturing environment. But all respectable foundries publish base defect-rates (related to their clean rooms), so you can use this info in your yield estimations. And of course, defect-rates vary from logic family to logic family. Bleeding-edge processes (90nm, 0.13u / 300mm wafer) have higher intrinsic defect-rates than older, more mature processes (0.18u, 0.25u / 200mm wafer.) Paradoxically, very old processes (0.65u and up) may actually have *HIGHER* defect-rates then newer processes, because the fab-line ages and deteriorates over time, just like any other manufacturing equipment.
The CAD-tools indirectly influence yield, because they affect modeling accuracy. If your design is 'conservative' (i.e. low-speed, small die size, etc.), a +/- 5% disagreement between your circuit simulations and the actual prototype-wafers won't kill you. On the other hand, if you choose to risk 'pushing the petal to the medal', then a +/- 5% disagreement could mean the difference (at the target clock-frequency) between a non-working ( < 5% yield), a marginally working (<20% yield)<, or a spectacularly working (>80% yield) device.
Experienced designers (which I am NOT...) digest this information, then figure out the best way to 'play the deck of cards they are dealt.' I say that cynically, because often times engineering teams have the joy of choosing between the 'less objectionable of two undesirables.' On the manufacturing side, that could look like the following: should we risk fabbing on a 300mm wafer line (higher chance of defects, but lower-cost if we sell > 10,000,000 chips), or play it safe on a 200mm wafer line (proven track-record, but higher cost/die.) On the design/architecture side, that could look like: "do we make a deep but turbo-clocked CPU (Pentium4), or do we make a shallower pipeline with more execution units (K7)?"
In an abstract sense, those choices are part of 'risk management' (economics), because they involve trade-offs between different cost/benefits. Some of these choices must be made EARLY in the design process (like 0.13u vs 0.15u vs 0.18u), because they severely affect every subsequent design step. Others can be postponed to the last possible second, (like 200mm vs 300mm, because mask-creation is traditionally started after tapeout.) Personally, I believe these design decisions play a more important role in overall device yield. In the overall project management, the foundry-choice (TSMC vs UMC, etc.), process-choice (0.13u, 0.15u, 0.18u), and usually frozen very early in the design-planning phase. Well managed/executed projects will leave a lot of time for the engineers to hammer out solutions for the obstacles posed by their design choices.
And feature creep is fun when it occurs late in the design cycle.
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argghh, I managed to digress several paragraphs without actually answering your question. Speaking generally, different 'products' in a logic fab-process can in fact be very physically different products. But does TSMC's 013G yield a lot differently from TSMC's 013LV? I do not know...
So we could accept that sense the RV350 have such good yields that the number of interconnect layers are low. Also sense the low-k dielectric process is so problematic (or has been.) we can take for granted that ATi uses fluorinated silicate glass unless TSMC has cleaned up the problems they were having. We can assume that the RV350 is not a "heavily-loaded e-Dram design based on yield rumors. I realize that the rumor may or may not be true based on the source I have little reason to doubt it but looking at the actual rumored yield (98% no less!) it makes you wonder.
GRRRR...that's not what I meant to say at all! You asked whether ATI's RV350 and NVidia NV30 were fabbed 'on the same process.' I tried to answer your question by pointing out some common rules of thumb. Those are just general guidelines which are applicable to *any* digital-IC design, nothing more and nothing less. I could point to my rules of thumb in order to engage in all sorts of wild RV350-speculation, but I won't...they're just rules of thumb, so they don't definitely say one way or the other, how RV350 was built.
