RSX patent?

[Dave Baumann]

I think most graphics chips have organised their memory accesses in tiles - the last one that I recall using scanlines was Voodoo2.

 

[j^aws]

There was another patent regarding tiles and small caches or something to store them, with an addressing mechanism. I wouldn't be surprised if they were designed to fit with the SPE's. We've been told Cell and RSX are cache coherant (right term?) and can share data directly. Must be a reason for this!

Yeah, I posted those patents a little while ago,

Double-buffering of pixel data using copy-on-write semantics


Desktop compositor using copy-on-write semantics

http://www.beyond3d.com/forum/showpost.php?p=511629&postcount=15

It makes sense to adapt the TurboCache as a 'tile cache'. The above patents refer to tiling 'buffers'.

 

[ManuVlad3.0]

The above tiling is interesting as the size is small enough to fit into SPE's local store!

[NOOB QUESTION]What this mean?
Could RSX uses SPEs+local store (all 7) like Xenos uses eDRAM?[/NOOB QUESTION]

 

[DeanoC]

We've been told Cell and RSX are cache coherant (right term?) and can share data directly. Must be a reason for this!

Where exactly have you read that? (cache coherant I'm talking about)

 

[Shifty Geezer]

No idea unfortunately. But I remember it clearly that some report from nVidia or Sony spoke of the cache's being 'identical' or 'shared exactly the same data' or something along those lines but in different language. Months back. I think this info was in concert with talk of the two platforms using the same FP system (not IEEE compliant) so the processing on one processor would be identical to the processing on the other. Maybe that's not what was said but it's what I understood the article to say!

Unless it's my dream fantasy existence getting the better of me (and my furry munchkin friends and their pet pixies tell me that's not the case).

 

[Xenus]

I remember someone, I think it was Ken , talking about the RSX and Cell interaction and saying that they could read directly each others data with no need of copying but I think it was refering to Cell being able to read the RSX's vram and the RSX being able to read system ram.

 

[Titanio]

I also thought it was said earlier that the FlexIO connection between Cell and RSX was cache-coherent..if that's the same thing. That FlexIO has a certain amount of coherent and non-coherent bandwidth, and RSX used only coherent links.

 

[j^aws]

[NOOB QUESTION]What this mean?
Could RSX uses SPEs+local store (all 7) like Xenos uses eDRAM?[/NOOB QUESTION]

Well, in a sense that could be analogous. Both SRAM local store and eDRAM are NOT caches but local RAM. Xenos would use super-tiling for it's backbuffer, whilst this patent suggest micro-tiling...

 

[ManuVlad3.0]

I also thought it was said earlier that the FlexIO connection between Cell and RSX was cache-coherent..if that's the same thing. That FlexIO has a certain amount of coherent and non-coherent bandwidth, and RSX used only coherent links.

My guess:

35G/seg coherent -> RSX
5G/seg non-coherent -> I/O (Blu-Ray, HDD...)

 

[slider]

http://ps3.ign.com/articles/662/662086p1.html

Slightly derailing discussions but, that link should clear up any doubts about the RSX. Only kidding. Rather thin "coverage". Has anyone seen anything else on this event?

 

[ManuVlad3.0]

Well, in a sense that could be analogous. Both SRAM local store and eDRAM are NOT caches but local RAM. Xenos would use super-tiling for it's backbuffer, whilst this patent suggest micro-tiling...

If this true, RSX isn't just a overclocked G70 after all.
Thanks for replay

 

[!eVo!-X Ant UK]

I am completely confused, can some one that is more technical than me please answear these question's?

1. What the hell does that coherant stuff mean??

2. what does this mean for PS3 good??bad?? what??? better games??? crapper games???

Im only here to learn people.

 

[BlueTsunami]

crapper games???

With toilet peripheral!

 

[!eVo!-X Ant UK]

With toilet peripheral!

lmao

 

[j^aws]

I am completely confused, can some one that is more technical than me please answear these question's?

1. What the hell does that coherant stuff mean??

It's to keep multiple caches consistent and from conflicting.

http://en.wikipedia.org/wiki/Cache_coherence

...and usually arises in NUMA architectures,

http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access

E.g. The PPE L2 'cache' in CELL would be 'cache coherent' with RSX's 'TurboCache'...

2. what does this mean for PS3 good??bad?? what??? better games??? crapper games???

Im only here to learn people.

Well, better games are more a testament to the Dev teams than 'cache-coherency'! But in a NUMA environment, it will only help...

 

[!eVo!-X Ant UK]

It's to keep multiple caches consistent and from conflicting.

http://en.wikipedia.org/wiki/Cache_coherence

...and usually arises in NUMA architectures,

http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access

E.g. The PPE L2 'cache' in CELL would be 'cache coherent' with RSX's 'TurboCache'...



Well, better games are more a testament to the Dev teams than 'cache-coherency'! But in a NUMA environment, it will only help...

Thank you for the response Jaw's. i will now read the links you kindly provided.

Thanks again..Ant

 

[3dcgi]

RSX accessing the PPE cache and vice versa doesn't mean cache coherent. Note that I don't know what PS3 is capable of I'm just pointing out that access and coherency are not the same thing.

 

[chachi]

RSX accessing the PPE cache and vice versa doesn't mean cache coherent.

Would the overhead even be worth it? You only have 512K of L2, you're going to be pushing *a lot* of pixels, why would you want to pollute your cache with that kind of data? This seems like people just wanting to checkmark buzzwords for the architecture even when it doesn't make sense.

 

[j^aws]

...Furthermore, the byte lanes are arranged into two groups of ports: one group of ports are dedicated to non-coherent off-chip traffic, while the other group of ports are usable for coherent off-chip traffic. It seems clear that Sony itself is unlikely to make use of a coherent, multiple CELL processor configuration for Playstation 3. However, the fact that the PPE and the SPE’s can snoop traffic transported through the EIB, and that coherency traffic can be sent to other CELL processors via a coherent interface, means that the CELL processor can indeed be an interesting processor. If nothing else, the CELL processor should enable startups that propose to build FlexIO based coherency switches to garner immediate interest from venture capitalists....

http://www.realworldtech.com/page.cfm?ArticleID=RWT021005084318

I think the cache-coherency comes from ISSCC 2005 and articles released around referring to FlexIO having coherent and non-coherent ports. Instead of a second CELL, we will have RSX instead...

Reading between the lines of Deano's earlier post ( a bit tricky, coz it was a one liner!), not sure whether he's suggesting it is cache coherent or not!?

 

[Shifty Geezer]

The info coming out of the Ninja Theory team is...perplexing. nAo doesn't know that PS3 uses OpenGL though the rest of us do, and Deano doesn't seem to know Cell and RSX are cache coherant as we all do.

How long until NDA's are past and devs can actually talk about writing for these systems? What's really the case with the people who actually have that hardware?? How come the devs don't seem to have the same perspective as the rest of us, who are only going by official spokespersons?