At 0.331 micron2, the 0.13-micron DRAM cell is smaller than the 0.422 micron2 cell of NEC's prior-generation process, and contributes to a 10 percent reduction in block size that reduces resistance in the circuit's bit lines.
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"The cells are actually not all that small," he said. In fact, Toshiba Corp. has built a 0.19 micron2 cell that it plans to use on its 100-nm eDRAM technology. "But we are concentrating on speed," Kishi said, "so we have to think of the right tradeoffs in other areas."
NEC and Atmos Corp. will jointly develop merged-logic embedded DRAM chips running between 400 MHz and 1 GHz. The companies hope the technology will replace SRAM in network processors, DSPs, ATM switches and routers.
The partners expect to start shipping volume quantities of their superfast logic-memory chips on the 130-nanometer process node by summer of 2002, said Hideya Horikawa, design-engineering manager of NEC Electronics Inc. They will prototype parts on the 0.13-micron process in the second half of next year and launch full production beginning in 2003, he said.