H. Peter Hofstee is giving a technical presentation on Cell right now, so I thought I'd post some notes for those who are interested. Probably most of this will be stuff we already know.
-Host mentions in introduction "in the Playstation 3, hopefully coming out this year", Peter cracks a smile.
-agenda: power wall, memory/latency wall, multicore and specialization, DMA and microarchitecture distinctions, thinks that work and don't work well, things for Academia to look at
-historical specInt single thread growth rate was 45%, but slowing dramatically
-memory wall: asynchronous loads point to non-homogenous cores, efficiency wall: specialized functions point to non-homogenous cores, power wall: reduced transistor power w/limit oxide thickness scaling, channel length and operating voltage points to multiple cores, reduced switching per function points to non-homogenous cores
- ceiling in terms of power - have already hit ceiling in terms of watts that can fit in a traditional computer form factor, need multi-core to progress, don't want much more than 250W in a consumer box
- motivation since 2001 was to "Support an introduction in 2005/6 - Challenge: structure innovation such that 5yr schedule can be met"
-sharing workloads across the network an important design motivation
-non-homogenous coherent chip multiprocessor allows attack on the "Frequency Wall" - deliberately designed for 4GHx, reduced to 3.2 w/ low operating volatage because power efficiency increases greater than cubically - "also helps that we spent 400 mil in that regard" (gets laughs)
-streaming DMA attacks "memory wall"
-potentially a collision between mainstream OS functions and streaming app/games, managed by hypervisor to allow realtime guarantees
-most programmers will not ("and I don't see in practice") use LS Alias available in main memory, since load balancing and scaling are difficult, instead refer explicitly to LS in SPEs
-token-based mechanism guarantees bandwidth at memory and IO chokepoints to real-time OS functions that need it
-Fundamental change for programmers - transition from demand-fetch to software-controlled prefetch - DMA lists to scatter and gather info from memory
-design "would have been flat-out impossible for a PC maker to pull-off" because performance is not as important to them
-everything goes into GPRs - branches, links, compare results - because don't like how higher-frequency processors these specialized registers bloat into stacks
-Q from audience: "this reminds me of the 'CDC 6600' processor with lots of little processors around the central processor". A: "the SPEs aren't really so little (compared to central core)- remember that on compute-intensive tasks they will outperform a Pentium 4"
-fetching from main mem to local store is not so bad - similar to cache miss, but you can have many things in flight
- shows Mercury development system, IBM blade
-future of Cell designs - may be a threat to "Windows" in desire for immerse, 3D interactivity in real-time with distributed, device-agnostic, collaborative apps
- "new types of applications (often real-time) made possible by a dramatic jump in performance - E.g. gesture and emotion recognition"
-thinks emotion recognition (with a camera - frown or smile) is a promising way of interacting with a computer
-Q: How are game devs doing? A: The Sony side knows more about specific game development progress...
-US export restrictions on supercomputers - "at some point we had a question whether all our employees could be allowed into the printing lab" jokes
