PCI-SIG and MIPI Alliance Reveal Mobile PCIe Specification

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PCI-SIG and MIPI Alliance Reveal Mobile PCIe Specification
ZoomPCI-SIG and the MIPI Alliance announced that they have begun procedural reviews of the Mobile PCI Express (M-PCIe) specification that will lead to its completion and availability. This technology will allow the PCI Express architecture to operate over the MIPI M-PHY physical layer technology and extend the benefits of this I/O standard to a variety of mobile devices such as tablets, smartphones and ultra-thin laptops.

The adaption of PCIe protocols operating over the M-PHY physical layer will provide a "low-power, scalable solution that enables interoperability and a consistent user experience across multiple devices." Additionally, the layered architecture of the PCIe I/O technology will facilitate the "integration of the power-efficient M-PHY with its extensible protocol stack to deliver best-in-class and highly scalable I/O functionality for mobile devices."


Could this mean an end to the dirt-slow eMMC we get even in the highest-end handhelds?
 
Could this mean an end to the dirt-slow eMMC we get even in the highest-end handhelds?
No.

I don't see what the relation between this and eMMC speed, they are slow in handhelds because of lack of parallelism because they only have a single IC with only a couple (correct me here) of memory dies. They are also directly connected to the SoC, so I doubt it's some sort of bottleneck in the interface itself.
 
No.

I don't see what the relation between this and eMMC speed, they are slow in handhelds because of lack of parallelism because they only have a single IC with only a couple (correct me here) of memory dies. They are also directly connected to the SoC, so I doubt it's some sort of bottleneck in the interface itself.


If it was that linear, mPCIe wasn't being implemented and they wouldn't brag about faster I/O speeds in the press release.
 
PCIe over a MIPI phy is probably just another PHY layer for PCIe, the way you can put PCIe over Thunderbolt. It means that existing higher level software stacks should just work.

I suppose one way or the other this can be beneficial for flash storage, but I highly doubt this is a first order driver for doing this. PCIe is too heavy a protocol to just serve ordinary flash chips.

Now why you'd want this over MIPI instead of the regular PCIe PHY is a different question. I believe MIPI PHYs are easier and lightweight (and lower clock?), so it should be a better choice in terms of power and design complexity than regular PCIe?
 
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