One trick on the R300...

[JonWoodruff]

One trick ATI used with the R300 to make ~107 million transistors practical on .15 micron is this:

Since defects per die increase geometrically as the die size increases, ATI designed the chip so that if there are defects found in one set of four pipeline, it can be turned off, and the chip can be sold as a four pipeline chip. ATI is able to harvest many of their failures and sell them as good chips. This way, ATI can get by with yields as low as ~60-70 per cent (lets pretend, just making up numbers), redeeming another 20 per cent for a lower-end product line.

Cool, huh?

 

[DemoCoder]

Cool, but every CPU, GPU, and RAM manufacturer does this already.

 

[Tahir2]

Does that mean that the Radeon 9500 is going to be a 4x1 pipeline? If that is the case then at the same clockspeed a GF4 would probably beat it in terms of speed alone.

Being 4x1 does that mean it will miss the DX9 spec of 16 textures per pass also?

 

[JonWoodruff]

What do you mean, DemoCoder? It takes special effort for a design to be flexable enough to cut it's losses and still work. I'm not aware of any CPUs that can cut off defective piplines and still operate (some do this with caches though.) I'm also not aware of it being done with graphics chips before (though NVidia enabled only one pipeline in the TNT2 Vantas, but those could be turned back on with software.)

This is one of the design features that allowed them to pull off the R300 on .15 micron. Without this feature, the yield would not likely be acceptable.

 

[OpenGL guy]

Being 4x1 does that mean it will miss the DX9 spec of 16 textures per pass also?

How does being 4x1 dictate how many textures per pass you can do? Answer: It doesn't.

 

[Tahir2]

OpenGL guy you might want to clear that up in this thread also.

http://www.beyond3d.com/forum/viewtopic.php?t=1985

However having half the pipelines, does that automatically mean it will take double the clocks to do 16 textures in a pass - keeping everything else equal? Just a general question rather than specific to the Radeon 9500.

 

[demalion]

What do you mean, DemoCoder? It takes special effort for a design to be flexable enough to cut it's losses and still work. I'm not aware of any CPUs that can cut off defective piplines and still operate (some do this with caches though.) I'm also not aware of it being done with graphics chips before (though NVidia enabled only one pipeline in the TNT2 Vantas, but those could be turned back on with software.)

Not pipelines per se, but I have an impression of something from nVidia doing this (GF 2 MX?), and a much clearer picture of certain early Radeon budget models doing this (VE). Also, I have a vague impression of CPUs with non functional FPUs (486 DX/SX?) and maybe caches (no specific example comes to mind for certain, though it might make sense for early Celerons and Durons) being used in this way. Seems desirable and smart for a company to this.

This is one of the design features that allowed them to pull off the R300 on .15 micron. Without this feature, the yield would not likely be acceptable.

It isn't the first design to stress a manufacturing process, I'd dare say, so I don't think this is unique was DemoCoder's point...and it seems valid to me. It does seem to indicate rather clearly what the 9500 will be, however, which wasn't quite clear before.

 

[OpenGL guy]

OpenGL guy you might want to clear that up in this thread also.

http://www.beyond3d.com/forum/viewtopic.php?t=1985

Looks like DaveBaumann took care of it

However having half the pipelines, does that automatically mean it will take double the clocks to do 16 textures in a pass - keeping everything else equal? Just a general question rather than specific to the Radeon 9500.

I won't comment on unannounced/released products, but if a 4x1 chip can do 4 textures in one cycle, then it seems like it should take 4 cycles to do 16. Similarly, if an 8x1 chip can do 8 textures per cycle, then it would take 2 cycles to do 16 textures.

 

[Dave Baumann]

You sure an 8x1 chip isn't taking 16 cycles to do 8 pixels?

[edit]: in fact isn't that more cache efficient - with 16 textures and pipeline combining you'll be swapping texture in and out the cache constantly; with all 8 pipes reading from each texture layer over (at best) 16 cycles you are getting better use of your cache(?).

 

[Tahir2]

Dave I think OpenGL guy was trying to be as ambiguous as possible whilst answering my question in full.

His answer is to my question is yes, from what I understand, it would take twice as many clock cycles if the pipeline is 4 compared to 8. Kinda obvious really but good to clear up for the layman (like me).

 

[ben6]

It's a little confusing sometimes as to as to number of textures per pass applied to a pixel , and number of textures per clock cycle. Make sure you delineate the difference. Otherwise you'll get oddities in reviews like Firingsquad saying the 8500 can do 3 textures per pass and 9000 6 textures per pass.

http://firingsquad.gamers.com/hardware/radeon9000/page3.asp

 

[DemoCoder]

What do you mean, DemoCoder? It takes special effort for a design to be flexable enough to cut it's losses and still work. I'm not aware of any CPUs that can cut off defective piplines and still operate (some do this with caches though.) I'm also not aware of it being done with graphics chips before (though NVidia enabled only one pipeline in the TNT2 Vantas, but those could be turned back on with software.)

This is one of the design features that allowed them to pull off the R300 on .15 micron. Without this feature, the yield would not likely be acceptable.

I'm not talking specifically about "cutting off pipelines" but deactivating defective portions of a chip and rebranding it as a different model. For example, 486DX's with defective FPUs were rebranded as 486SX. Every major chip since Pentium has sold different versions based on how much cache was defective. TnT Vanta software disabled one pipoeline (it only has 2). The fact that it could be turned back on is irrelevent since it must have failed a unit test somewhere. Perhaps some software hack could turn back on some of the 9500's reduce functionality if the defect in the pipeline wasn't too serious, or a testing failure.

NVidia is selling multiple versions of the MX, one which 64-bit bus, one with 128-bit bus, and some variations in between. Could these be chips with bad datapaths somewhere, or a defective memory controller?

All I'm saying is, for years, designer have been designing chips to "degrade gracefully" in the face of defects. It was one of the breakthroughts that allowed DRAM prices to fall so significantly. I just don't think it's unique. No one wants to "throw away" fabbed chips into the garbage can if some functionality can still be sold.

 

[Freon]

The fact that it could be turned back on is irrelevent since it must have failed a unit test somewhere.

As with speed binning, demand doesn't dictate yield and supply. Change out "must" with "possibly" and I would agree.

In response to one of the other posts, the Duron is a different chip. It is actually physically smaller than a normal Athlon with a lower transistor count. But the theory is still possible when it comes to Celeron/P3 Coppermine chips. The chips are the same size and Intel even quotes the same transistor count.

 

[fresh]

You'll also see chip designers put redundancy into their designs. So maybe instead of having 4 vertex pipelines, they'll put 8 so that you can have 50% of them fail, but still have a good chip. [That's just an example].

 

[RussSchultz]

It would be cheaper in the long run to have exactly as much silicon used as needed, and solve the problem in the yield side.

For example, if your yield is 80% with no backups, and 86% with backups, but the backups take 10% die size...you're not gaining anything and you're actually losing money.

Of course, the numbers are just hypothetical and might not work out that way, but I suspect something as big as a pixel pipe would be too expensive just to throw another on for redundancy.

As for RAM and such, repairable ram is all the rage. For flash, ECC that can correct multiple bit failures is what's upcoming.

 

[Bigus Dickus]

It would be cheaper in the long run to have exactly as much silicon used as needed, and solve the problem in the yield side.

For example, if your yield is 80% with no backups, and 86% with backups, but the backups take 10% die size...you're not gaining anything and you're actually losing money.

Of course, the numbers are just hypothetical and might not work out that way, but I suspect something as big as a pixel pipe would be too expensive just to throw another on for redundancy.

As for RAM and such, repairable ram is all the rage. For flash, ECC that can correct multiple bit failures is what's upcoming.

Well, it's not like they're doubling pipelines "for redudancy." If all 8 pipelines work, it lives on as a 9700. If one is defective, a block of four is disabled and it becomes a 9500. By doing this, dies what would have been scrapped are not.

 

[noko]

Well what happens when the demand for the Radeon9500 exceed the defective R300 chips? Will ATI purposely default good Radeon9700 chips to Radeon 9500 status? Since the Radeon 9500 is surpose to be mainstream and at a much lower cost then the number sold should be more then the Radeon9700 anyways. So is this really viable for ATI to do if Radeon9700 good chips are around 80%, if so then many of the Radeon9500 chips will be crippled for no reason except to sell a cheaper card.

 

[3dcgi]

Well what happens when the demand for the Radeon9500 exceed the defective R300 chips? Will ATI purposely default good Radeon9700 chips to Radeon 9500 status? Since the Radeon 9500 is surpose to be mainstream and at a much lower cost then the number sold should be more then the Radeon9700 anyways. So is this really viable for ATI to do if Radeon9700 good chips are around 80%, if so then many of the Radeon9500 chips will be crippled for no reason except to sell a cheaper card.

The better yeilds Ati gets the more likely they will lower the 9700's price to shift the demand to the more expensive card.

 

[Mintmaster]

One trick ATI used with the R300 to make ~107 million transistors practical on .15 micron is this:

Since defects per die increase geometrically as the die size increases, ATI designed the chip so that if there are defects found in one set of four pipeline, it can be turned off, and the chip can be sold as a four pipeline chip. ATI is able to harvest many of their failures and sell them as good chips. This way, ATI can get by with yields as low as ~60-70 per cent (lets pretend, just making up numbers), redeeming another 20 per cent for a lower-end product line.

Cool, huh?

By the way, what's your source? What you say makes sense though.

 

[elimc]

What do you mean, DemoCoder? It takes special effort for a design to be flexable enough to cut it's losses and still work. I'm not aware of any CPUs that can cut off defective piplines and still operate (some do this with caches though.)

The P4s do it all the time. When part of a cache doesn't work, they half the cache and label it as a celeron. It keeps profits up for the company with what would otherwise be a useless chip. And from what I understand, caches are generally the main point of failure on the P4.

Well what happens when the demand for the Radeon9500 exceed the defective R300 chips? Will ATI purposely default good Radeon9700 chips to Radeon 9500 status?

Possibly. We haven't yet seen the 9500, and it might have its own process, which would make sense considering that parts of the GPU were supposedly full custom.