Panajev2001a said:
According to the patent, none of them is a cache...
I don't have the patent stored in full in my head. My point is, when a processor of Cell is going to work on a piece of data it's going to get fed that data through DMA, first from eDRAM, which in turn is fed by main RAM. The room that data occupies is not going to be swapped with some other piece of data first, it's just going to get written over which means you need copies of EVERYTHING in full in main RAM, even if you have 32MB of extra on-chip eDRAM.
And they will function the way the programmer use them...
Programmer will still use them to buffer pieces of data that comes from main RAM, how else would the machine function?
Do you expect a 400 MHz ( quad-pumped to 1.6 GHz ) FSB for the Pentium 4 in the Xbox 2 yelding 12.8 GB/s for CPU bandwidth alone ?
Yeah. Intel's already put 400MHz FSB on their roadmaps.
Well... the Pentium III in the Xbox only had a 1 GB/s bus and you are expecting a >12x increase...
So what? P4 when released had FSB that was about 3x faster than that silly celery in the XB. As far as I'm aware, there was no celery with 133MHz fsb at the time of the XBs release, Intel simply made one by changing the multiplier of an ordinary celly!
I am not saying that by 2005 Intel will not double once again the FSB, but that would be in 2005 a high-endconfiguration
For PCs yes, but there's nothing high-end about changing a multiplier. Selling M$ a 400MHz-bus as opposed to a 333MHz-bus (a step we're going to see early next year I believe) is just a matter of changing the multiplier of the processor. There would be no extra cost involved.
In 2001 a Pentium III 733 MHz with a 1 GB/s FSB cannot be described as being high-end...
As far as celery bus interfaces went, it sure was high-end.
*G*