D
One aspect it seems none have made a comment about is how the TDP-TBP has increased for the V100 from 300W to 350W with the SXM3.
The HBM2 memory increase is only partially to explain for the increase.
Considering that power usage grows faster than performance and more HBM2 probably using more power, it should be max 17TF, if even thatSo Titan V and V100 PCI-E are rated for 14 TF and 250w, while the V100 SXM2 is rated for 15.7 TF and 300w. And now we have a V100 SXM3 rated for 350w with how many TF? 18? Or Is it just for the extra 16GB HBM2?
NVSwitch chips are separate (outside of the SXM3) and with their own heatsink, each of the switches are somewhere between 50W to 100W.If this isn't somehow lumping in the power consumption of the switch chips, there could be extra power consumption from the presumably higher IO utilization of having full link bandwidth to any other GPU without becoming bottlenecked or blocked like in the prior topology.
NVSwitch chips are separate (outside of the SXM3) and with their own heatsink, each of the switches are somewhere between 50W to 100W.
Basically they all connect through the NVLink baseboard.
Those switches also work out to ~75W per GPU (6 switches @ 100W to 8 GPUs). A standard ~275W card consumption per GPU with additional <75W off chip as an IO buffer (NVSwitch) would give the ~350W peak figure. They probably lumped in the network cost per GPU. It's also not inconceivable they are powered inline with the 75W PCIe connector spec. Move the drivers off the GPU onto the switch chips with tighter control if only having to drive a signal a matter of centimeters and not meters.NVSwitch chips are separate (outside of the SXM3) and with their own heatsink, each of the switches are somewhere between 50W to 100W.
Basically they all connect through the NVLink baseboard.
Maybe it could be a misunderstanding between Nvidia and a few people.I'm leaving open the possibility that there was a misunderstanding of the per-module consumption within the DGX-2 system, in the absence of a cited Nvidia statement. That aside, the SXM2 modules used in the prior product only used 4 links for connectivity versus the 6 for DGX-2, which can contribute to higher power consumption.
The nextplatform article tries to estimate that the 32 GB of HBM in an SXM3 takes the memory power consumption from 50 to 100 W. The 50W for 16GB may be in the ballpark (I've seen estimates for Vega's HBM at 20-30W), depending on whether Nvidia is still using HBM2 that's been volted above the spec's 1.2V. Crediting the doubling capacity to 32GB for another 50W seems dubious. Capacity alone has a much lower contribution versus the actual access costs, which makes me uncertain there haven't been other misunderstandings.
Of note, Nvidia's SXM2 spec has 16 and 32 GB capacities listed under the same 300W TDP.
SXM2 is 300W not 275W though.Those switches also work out to ~75W per GPU (6 switches @ 100W to 8 GPUs). A standard ~275W card consumption per GPU with additional <75W off chip as an IO buffer (NVSwitch) would give the ~350W peak figure. They probably lumped in the network cost per GPU. It's also not inconceivable they are powered inline with the 75W PCIe connector spec. Move the drivers off the GPU onto the switch chips with tighter control if only having to drive a signal a matter of centimeters and not meters.
Just to say SXM2 V100 has 6 bricks-links (NVLink2), was the original/SXM2 Pascal with only 4.I'm leaving open the possibility that there was a misunderstanding of the per-module consumption within the DGX-2 system, in the absence of a cited Nvidia statement. That aside, the SXM2 modules used in the prior product only used 4 links for connectivity versus the 6 for DGX-2, which can contribute to higher power consumption.
The bandwidth is still 900 GB/s, from the GTC 2018 keynote (14.4 TB/s across 16 GPUs).Did Nvidia officially release the HBM2 memory clock rates for SXM3 yet?
Maybe they have increased them to the manufacturer spec.
That is the NVSwitch rather than the HBM2 memory; 18 ports at 50GB/s gives the 900 GB/s.The bandwidth is still 900 GB/s, from the GTC 2018 keynote (14.4 TB/s across 16 GPUs).
Then where did the 14.4 TB/s in the keynote come from? (Because that's how I calculated 900 GB/s.)That is the NVSwitch rather than the HBM2 memory; 18 ports at 50GB/s gives the 900 GB/s.
LOL yeah good point and sorry (was referencing other data while reading your post), I had only seen it referenced before in terms of the NVSwitch.Then where did the 14.4 TB/s in the keynote come from? (Because that's how I calculated 900 GB/s.)