That won't be a static power consumption though. It's just a matter of what power profile Nvidia configures. What I'm suggesting is that the IO power consumption is pushed onto a separate chip in some configurations. Increasing the distance between chips for example will increase the energy expended. Leaving the switch chip to absorb most of the work of driving IO over longer distances and capacitance. Effectively an inline buffer/repeater. In the presence of a switch, the power usage of the GPU may drop and the 300W figure somewhat arbitrary.
Not sure I follow or how you feel this affects SXM2 (this is non-NVSwitch model), although I agree they subtly change the envelope which is why TDP does not usually increase due to memory capacity; mentioned this in response to another poster earlier.
What your quoting from me is the actual TDP-TBP that Nvidia always uses for the actual GPU board or actual SMX card; it must include all aspects of the board VRM-stages-GPU-memory-IO and always has recently with how Nvidia reports their TDP-TBP.
The power behaviour will not be that different between a 6 brick hybrid mesh to a 6 brick-to-NVSwitch and yeah the NVSwitch will have higher power demand.
But it will not reduce the accelerator's requirements or physical characteristics to a point it would be of notable significance; some SMX3 will be very close to a NVSwitch some further away and made even more complicated that each brick for all dGPUs are aggregated across various NVSwitches.
Point is this would not be possible if the variance was that great from an EE physical transmission perspective.
The NVSwitch is completely separate in context of TDP with its own.
Remember the 300W is the SMX2 and not NVSwitch configuration (that is SMX3), that said TDP by Nvidia is quoted at maximum spec boost-configuration and yeah it is difficult to get completely accurate due to the very dynamic nature of the power-thermal-performance/clock management and IO, but usually Nvidia is pretty good with their figures.
However it is all relative between the Nvidia GPUs/accelerators as can use their methodology and apply it to all their modern dGPUs and accelerators (whether SMX2 or SMX3 or PCIe).
The 300W (or 250W for the PCIe models) TDP is also complicated due to how one measures (the more sensitive the interval say below 10ms the more variance you will see) and also what process (compute FP32-FP64, rendering-gaming,etc) one uses to measure the TDP, but that is a different topic and covered in depth in past when discussions about the TDP-TBP of 480 and 960.