Nvidia Volta Speculation Thread

So what advantage does Stacked memory hold over standard memory ? less latency? faster access times? or just plain old increase in frequency ?
Most of the above all at once, probably. Except increased frequency, as that becomes problematic as you keep piling on the megahurtses.

Probably it will rather be a very wide bus instead, with significantly lower frequency compared to modern GDDR. That way you won't need a giant signal driver on the memory IC taking up a huge portion of the die, and also not the same on the ASIC side.

Main question will rather be how you'll cool your stack. Now, NV seems to be stacking memory on the substrate rather than straight on the GPU, so it is not likely to be an issue. However to fully realize the performance benefits of stacking, eventually we would have to put the memory straight on the die, and then heat becomes quite an issue.
 
I think Einstein was/is planned for 10nm, so Volta would be the chip that falls between Maxwell and Einstein. I imagine it will just be a refinement of Maxwell with the largest benefit being the stacked memory.

Indeed, Einstein is the architecture of the Echelon chip that was announced, to be released in 2020, be made on 10nm and be used to build exaflops supercomputers. A slide conceptually representing it said it has "memory cubes" along it.
 
So what advantage does Stacked memory hold over standard memory ? less latency? faster access times? or just plain old increase in frequency ?

Assuming memory stacked on a silicon interposer, the primary gain is to make wider buses cheaper.

The reason we don't have 1024-bit buses today is that they are cost prohibitive using the standard interfaces. The idea of 2.5d integration is to move from normal pins and traces on a pcb into traces on a silicon interposer, that are much, much thinner and smaller, and much cheaper per pin.

The power savings come from the fact that when you can use as wide of an interface as you like, you can scale down the interface frequency and still get more bandwidth. Lower latency comes from shorter distances to memory, and also from less need to boost the signal so that it can travel on the thicker wires.
 
Maxwell is pretty much done, GM10x released and soon in the future, GM20x.

Volta is Nvidia's next major architecture and won't be out for a few more years, pretty much it's gonna have to target DirectX 12 now.
 
We will see on March 20. It all depends on what really DX 12 is.
It could be that not has more "functions" but better use of the ones we have.
 
Indeed, DX12 may support Maxwell and even Kepler/Fermi for all we know. Then again, a new more advanced hardware feature set that requires a new GPU architecture would also be very nice. Perhaps they could do both. i.e. support older GPU's in terms of the overhead improvements but also support a new feature set on GPU's that support it.
 
Maxwell is pretty much done, GM10x released and soon in the future, GM20x.

Volta is Nvidia's next major architecture and won't be out for a few more years, pretty much it's gonna have to target DirectX 12 now.

It depends on what hardware features are required for DX12. For all we know, Kepler might be capable of supporting it; or Volta might be incapable of it, as 2 years could prove too little to add potential major features.
 
HMC is boring, it's not even designed for interposers ... in the end it's still a narrow bus DRAM, just a very expensive one with very high signalling rate (too high for the DRAM chips I imagine, they currently have a very expensive 32 nm logic chip on the bottom of the stack).
 
I thought the shorter traces/interface would enable higher speeds?
Generally yes, but DRAMs scale very poorly in frequency, due to the fundamental physics involved of their basic function...

Very high signalling rates are used today to gather up the I/O from large, slow, wide DRAM arrays inside a DDR3 or GDDR5 chip and transmit the data over a feasibly narrow interface to the host IC (as you either couldn't fit a 1kbit DRAM interface on an ASIC at all, or not be able to do it in a cost-effective manner.)

With stacked DRAM, 1+kbit memories become doable (the Sony Vita already has this, for its stacked video RAM), and the need for very high data rate interfaces simultaneously go away, since you may as well be talking to the DRAM array directly at its native speed, without much or any inbetween logic...
 
The "Stacked DRAM" picture they're using is 1:1 Hybrid Memory Cube -demonstration picture - incidently video cards have been speculated as the 1st platform to utilize HMC in retail products.

With the HMC 2.0 specs that were released recently, HMC is allowing up to 480GB/s bandwidth per HMC-module, with modules ranging from 2 to 4 GB of memory.
 
Volta has been renamed Pascal

http://www.anandtech.com/show/7894/nvidia-gtc-2014-keynote-live-blog

http://www.forbes.com/sites/jasonev...n-gpu-pascal-to-incorporate-new-technologies/


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From the roadmap images (page 1 and here) I see that Pascal is pushed out well into 2016 while the previous roadmap showed something at least looking like Q4 2015.

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Yes, it looks like they scrapped Volta and Maxwell is now an architecture being used for over 2 years like Kepler before it.

Could it be that nVidia is changing its roadmap because of this?

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I'm wondering the same thing. Jokes about volts and power consumption, perhaps?

Volta is a great reference to the first cell batteries, it symbolizes the breakthrough in using very high bandwith stacks of memory dies. They both are stacks.

But there may be connotations of being associated with an early, first generation product :) :
However, this cell also has some disadvantages. It is unsafe to handle, since sulfuric acid, even if diluted, can be hazardous. Also, the power of the cell diminishes over time because the hydrogen gas is not released. Instead, it accumulates on the surface of the zinc electrode and forms a barrier between the metal and the electrolyte solution.
 
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