Nvidia Post-Volta (Ampere?) Rumor and Speculation Thread

Discussion in 'Architecture and Products' started by Geeforcer, Nov 12, 2017.

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  1. CSI PC

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    Worth noting though Nvidia initially launches the higher models 1st so that helps to offset some of the yield level related costs and especially when considering Tesla accelerator.
    But whatever node they go with, it will need to last at least 17 months when one considers the cycle of replacing previous model, and needs to be applied across the whole of their range Tesla/Quadro/Geforce, Tegra can be differentiated.
    If the new cycle does not start until March-April, then they are definitely in no mans land in terms of node tech size from TSMC and 7nm starts to make more sense even with a higher cost as it will take 6-9 months to fully roll-out the whole range starting with the high performance/margin and working down.

    We know Samsung and TSMC will diverge at 7nm, with TSMC going with what seems multipatterning that can be brought to market quicker (not necessarily better): http://semiengineering.com/kc/knowledge_center/Multipatterning/196
     
    #61 CSI PC, Dec 22, 2017
    Last edited: Dec 22, 2017
  2. Samwell

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    I think we will see GA102-GA106 on 12nm. GP107 on the other hand was launched a bit later than the others. I wouldn't be surprised to see this chip as a test gpu on 7nm. Starting with a monster gpu on 7nm will not only depend on the process itself, but also on ram technology. Without HBM3 the bandwidth improvement possible seems too small for a big compute gpu. But HBM3 won't be ready before the end of 2019.

    As AMD wants to move fast to 7nm, nvidia might get some problems this time beeing competitive with 12nm against 7nm in the beginning. AMD might move to 7nm early 2019, but for nvidia this won't be possible. Apple takes all the first 7nm wafers from tsmc and qualcomm is also back at tsmc 7nm. Before mid 2019 nvidia won't get the wafer allocations they need.
     
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  3. Bondrewd

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    More, well, exotic memory standards do exist.
    UM-1, for example.
     
  4. Digidi

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    Titan V ist now out. Any guessing what ampere will looks like?

    I think 6 Geometry engine are enough for 6000 shaders if you see titan V.

    Maybe they build 8 Geometry engines with 8000 shaders at 600mm^2
     
  5. Kaotik

    Kaotik Drunk Member
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    TSMC's so called 12nm was supposed to be 16nm but competition having 14nm made them rename it 12 nm (just like glofo now renamed their "2nd gen 14nm" 12nm).
    I don't think previous processes can be applied to this "switch"
     
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  6. Kaotik

    Kaotik Drunk Member
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    I think you're overestimating how much FP64 and Tensor Cores take up space if you think ~8000 shaders could fit ~600mm^2 at current processes
     
  7. Benetanegia

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    There's also NVLINK and arguably half or reduced register file. But yeah, 8000 seems way too much.
     
  8. CSI PC

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    Simpler way to calculate FP64 space required is to look at the GP100 and GP102; both with same number of FP32 CUDA cores (albeit GP100 never launched fully enabled but this will probably apply to V100 IMO).
    P100 is 610mm2 with 3584 cores and 15.3B transistors, while the Titan X is 471mm2 with 3584 cores and 12B transistors - both with reduced enabled cores.
    Of course this only focuses on the FP64 cores and not helpful with regards to Tensor cores but that should be smaller and is a lot less number of cores.

    Yeah I appreciate this is a very simplistic view possibly made more complex with the mezzanine but probably closest one can get to understanding the space requirements, and also then allowing potentially for the 'GV102' or whatever model it is named to have fully enabled SMs/cores (depends upon size of the die).
     
    #68 CSI PC, Dec 24, 2017
    Last edited: Dec 24, 2017
  9. Ailuros

    Ailuros Epsilon plus three
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    Depends on the perspective; under a different perspective Pascal isn't necessarily a "real next generation" compared to Maxwell either. With a KISS approach the majority of performance increases comes from architectural changes and the smallest percentage from process technology. The latter being increasingly problematic it's less of an issue since it's not a singled out side effect for one IHV only.

    That said and since the true major point of interest would be any sort of GP104 successor (if the next generation is truly called Ampere then let me use "GA104") then a hypothetical GA104 can get away with a few farts over a double digit billion transistor budget, fits easily into anything TSMC 12FF and can deliver a sizeable enough performance increase to deserve a "next generation" description. Any chip bigger than that for whatever purpose won't be be even remotely close at any >$700 MSRP and therefore chip size and manufacturing cost is quite a tad less relevant.

    What I'd expect as a layman for an upcoming architecture as the rumored Ampere would be a re-shuffle of units within SMs and a way tighter layout within ALUs amongst others, if that makes any sense at all that is ;)

    As a sidenote it's good to hear from you after all those years ;)
     
  10. Pixel

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    So the latest rumor going around youtube and wccftech is that Ampere is going to offer a 70-80% jump in performance. So the 2060 will be roughly equal to the 1080 in performance.

    Its almost not worth mentioning because its too unrealistic. This ain't the jump from 28nm to 16nm FF.
     
  11. Bondrewd

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    I mean, you can achieve that with bigger dies.
    What stops NV from making bigger dies?
     
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  12. McHuj

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    I wouldn’t expect the 2060 to beat the 1080ti, but the 2070 should be really close. That has been the normal trend the last two times. Pascal got there with new help of a new process, but Maxwell manages to do it on the same node as the previous gen.

    It’s been almost two years since Pascal so my expectations have risen. Architectural improvements, bigger dies, and a slightly improved processes could easily add up to that performance level.
     
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  13. nnunn

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    Also, given (a) sufficient power savings from re-re-re-worked fp32 clusters, and (b) the need for bandwidth by both miners and VR, what chance NV might have managed to slip back in a proper 512 bit bus... but this time to 18 Gbps GDDR6 :runaway:

    Some card has to be first over the 1.0 TB/sec barrier... why not a new, consumer-focused holodeck engine?

    /wishful thinking from a guy saddled with bandwidth-limited fp32 kernels
     
  14. Pixel

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    Fair enough, their Pascal dies are fairly conservative. But I remember reading over and over about industry observer hulabaloo about cost per transistor not decreasing much at these smaller nodes. Guess those fears were overblown and TSMC and others overcame the challenges that increase fab complexity could bring to operating costs.
     
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  15. Frenetic Pony

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    They're not really overcome, this is late in the cycle comparatively for "14nm" or whatever you want to call it and so reliability goes up. Cost per transistor also used to go down a lot more than it does now, but that's not to say it doesn't go down. Combined with Nvidia charging a hell of a lot for their huge dies like Titan V, well... Point is just because you can make bigger cards, doesn't mean the average consumer is necessarily getting a deal.
     
  16. Megadrive1988

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    Hmmm.

    https://www.reuters.com/article/us-...s-shoot-prices-through-the-roof-idUSKBN1FT2AW


    https://translate.google.com/transl...a/news/hardware/2018-02-13/121786/&edit-text=
     
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  17. Grall

    Grall Invisible Member
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    To amplify the rumormongering echo chamber effect, I'll mention that Techpowerup also has a blurb stating much the same. :) They seem to have gotten their infos from the Reuters blurb you linked to.
     
  18. Picao84

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    In the case of Turing, there was already a T generation for Tesla, so would we have GAT1xx or would they repeat GT? Truth to be told all GT parts were GT2xx, so they could go with GT1xx.
     
  19. nutball

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    Turing would be more apt for a deep-learning-oriented variant, would it not?? (Not that codenames have to make any fucking sense, as AMD seem keen to demonstrate).
     
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  20. CarstenS

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