There was no GT4e with Haswell or Broadwell.
There is a Sky Lake 45W Core i5 with the GT4e too.
I keep seeing this misconception from multiple posters that fast INT8 and INT16 support is new to Pascal. It's not. All Kepler, Maxwell, and Pascal parts have the key 4x rate INT8 MAD and 2x rate INT16 MAD, plus other functions like min/max and shift. These are commonly used in CUDA and are labeled "scalar video instructions".
Instead of "raster" I think it would be better to think in terms of "work group and work item despatch and scheduling". Instead of ROPs you might think of "global atomics" and general memory operations. And instead of TMU-filters it's better to think of algorithms that are served by the texturing cache hierarchy/swizzling. All of these things are relevant to pure compute.
Part of the reason for my question was: imagine that the priority for the chip was double precision. Is it possible to put more DP into the chip, regardless of SP and HP and stay within the power budget?
Maybe this is the real reason?
That's only if you think of SP as being like the actual HP implementation. Intel uses ganging. In other words, the SP is two real lanes and DP is two lanes working in concert.
No doubt, power has been a tight constraint for quite a while now: but NVidia keeps telling us that computation is not the power hog, it's routing data into and out of the ALUs. Routing and area must interact. It seems likely to me that routing either to SP or DP ALUs and then routing results back hinders power-efficiency (larger overall candidate area spanned by the data).
Isn't that precisely what GP100 is?
I would expect a modern design to switch off the paths that aren't required in SP mode. Intel's design (being multi-precision) is the obvious place where this should be the case. But does anyone know if that's what's happening?
Absolutely. I talked about this earlier (NVidia doing the noble thing, Intel buying bums on seats.)
Volta isn't that far away it seems, so that all sounds reasonable.
Late here so cannot look back at reference info for it, but a good card to possibly look at from that perspective is the original Kepler GTX Titan as it had two modes for DP and in the 1/24 ratio this gave higher clock speed, while with its full DP support enabled of 1/3 this reduced the clock.
Well I think that would sort of work - like ddr3 does today with 940m (I'm still quite amazed what gm108 gets out of this no-bandwidth solution). Fastest ddr3 used on these chips is 1000Mhz (often just 900Mhz) - so 50% more with ddr4-3000, plus the alleged 20% improvement due to better compression should help quite a lot (so, a gp108 chip would be similarly bandwidth limited as gm108, though that would also depend if it's just higher clocks or adding another cluster).
That's not what I'd call "take gddr5 serious". I've seen exactly zero notebooks with a 940MX and featuring gddr5 memory - yes the option is there but it's optional. If nvidia is serious about this they need to give it a higher model number otherwise there's plenty of evidence (not just with this chip) noone is going to bother (not that things are any better in the red camp wrt ddr3/gddr5 variant naming). The fastest gm108 part to date is still the one in the surface book (albeit with just 1GB gddr5 memory).
Yes, possible. clamshell configurations don't seem to be popular in the low end segment. I absolutely agree though it would make sense...
I think you're probably right the graphics might be mostly the same.
Actually I have seen a few 940MX with GDDR5..but I totally agree..they need to stop making it optional and separate the DDR3/4 & GDDR5 variants with different model nos, say 1020M and 1030M.
Problem with GT3e already in 14 nm is: Power is 40-50is watts for the GT alone under load. So mobile parts won't have a hard time beating it perf/watt.
Interesting! Any reason why there's no 32-bit sort for the Quadro? Would it skew the diagram's scale?I've been hacking some compute kernels on an Intel Broadwell GT3e lately and it's a fascinating GPU.
I'm still tracking down some seemingly odd GEN codegen for 64-bit load/stores to local memory but, otherwise, for my use case performance seems to be competitive with a similarly spec'd discrete Maxwell v1 GPU.
FP16 support has not yet shown up in the Windows driver but in theory it should enable double-rate FMA throughput (16 FP16 FMAs/clock per EU x 48 EUs x 1.15 GHz = 1766 FP16 GOPS).
I will have my FP16x2 support in this life or the next!
Those are the programmable parts, yes, even in DP mode it's not only the ALUs and PRFs working full time. But there's quite a bit of FF in those stages as well which won't be consuming much energy while the chip churns through DP warps. Hence i explicitly mentioned raster, not whatever-threaded command processor.
That's a tough nut to crack. I'd say: Insufficient data as of yet.
Of course, but wasn't that what you were proposing?
It surely is a delicated balance.
AFAIR, no one yet has gotten an answer out of Nvidia about whether or not the DP units are actually inside some select SMs (all of them in GP100 for example) and are in fact just fatter multipliers and adders taking over, sharing the datapaths of two SP-units once it's a DP-Warp. So technically, they would fulfill what nvidia termed "separate units, off to the side" (which is their official and most detailed answer yet, AFAIR)
Not with FP32 and FP64 in separate ALU blocks. What I meant here was what you talk about later: Multi-precision ALUs throughout the chip, sacricifing a bit of FP32 and power-in-FP32 for maximum FP64. It would also make the more sense, the closer delivery date for the government funded exascale architecture looms.
Obviously, but it's only clock- not power-gating I would guess. Power gating inside each multiplier (and probably adder) seems quite (rather prohibitevly expensive in terms of transistor budget.
That may be the case - if GPUs do not evolve a bit as well in the meantime. I don't know though were exactly FPGAs sit on the 3d-curve of throughput, power and configurability. On any two of them, they are pretty strong, but does that apply for the third dimension as well?
Maybe not for long.
