D
Deleted member 2197
Guest
MareNostrum 5 will also be the fastest AI supercomputer in the EU once in service.
Nvidia Hopper Speculation, Rumours and Discussion
DegustatoR
Legend
Designing Arithmetic Circuits with Deep Reinforcement Learning | NVIDIA Technical Blog
Learn how NVIDIA researchers use AI to design better arithmetic circuits that power our AI chips.
developer.nvidia.com
I told it 6 months ago and it's one of the reason of Hopper/Ada big improvement in circuit design, clock speed and power consumption. It's an important competitive advantage over AMD on this generationDesigning Arithmetic Circuits with Deep Reinforcement Learning | NVIDIA Technical Blog
Learn how NVIDIA researchers use AI to design better arithmetic circuits that power our AI chips.
DegustatoR
Legend
Nvidia has been using ML in h/w design for some time now AFAIK. Hopper certainly isn't the first.
They used very few rudimentary tools on Ampere gen. Hopper / Ada is when it starts really to make a big impact, along with their in-house Selene supercomputer
AI designing better AI. I can see this ending well.
Nebuchadnezzar
Legend
This is just physical layout design, AI isn't writing RTL.
That doesnt make any sense. AMD has only started recently using DL for designing their chips. There was a news that they are using Google's infrastructure: https://www.googlecloudpresscorner....de-Additional-Scale-for-Chip-Design-Workloads
In the linked article, NVIDIA claims that their reinforcement learning did circuit planning 25% smaller than a leading EDA tool.
Of course that could be a hand picked best cast scenario, but again in the article it's claimed that Hopper has nearly 13,000 instances of AI designed circuits. If the advantages in these instances are, say 15%, that's quite significant.
If we take a closer look at their paper, the so called "commercial EDA tool" is better than PrefixRL at optimizing circuits for the lowest delay times.
What's the comparison like for other process technology outside of 8nm ? PrefixRL is strictly limited to optimizing parallel prefix circuits as well so you still need EDA tools for many other circuits in hardware design ...
I guess AMD is using off the shelves Cadence and/or Synopsys ML optimisation plugins :
AI / Machine Learning
Cadence has already established a leadership role in software and IP, having implemented machine learning in current products to improve productivity and performance and ultimately, more automation through intent-driven design.
www.cadence.com
AI & Machine Learning Design Solutions | Synopsys
A new breed of Autonomous AI-driven Applications dramatically changes the exploration of choices in design workflows, offering a leap forward in designer productivity.
www.synopsys.com
Nvidia has his own plugins and tools:
Silicon Express Lanes: AI, Acceleration Pave Fast Routes for Chip Designers
Machine learning and accelerated computing are giving engineers ways to design better semiconductors faster, according to research detailed in a keynote by NVIDIA’s chief scientist.
blogs.nvidia.com
Have you actually read the article you linked? It has absolutely nothing to do with DL or AI or any such thing, it's just telling that AMD has decided to use Google for additional capacity on top of what they had. The hardware they're using in the Google Cloud is nothing special either, just Milan Epycs.
https://wccftech.com/nvidia-hopper-...cuits-smaller-faster-power-efficient-designs/
NVIDIA’s Bleeding-Edge Hopper GPU Feature 13,000 Instances of AI-Designed Circuits Leading To Smaller, Faster & Power Efficient Designs
how many circuits AD has in total
?
DavidGraham
Veteran
Hello! Yes?
you know, 13k circuits , overwhelming
)
D