NVIDIA GT200 Rumours & Speculation Thread

[jimmyjames123]

Yup, definitely true. The one thing that I'm really looking forward to seeing is how well PhysX will be utilized on the NVIDIA cards moving forward. I imagine that NV is working like mad with the game developers to see their vision come to light in the future.

 

[Berek]

1100Mhz GDDR3 (2200Mhz effective) gives 140.8GB/s on a 512bit bus.

Thats quite a bit higher than the Ultra with only 103.7GB/s.

If these specs are true this thing soumds like a beast! 1.08 TFLOPS of shader power at 1500Mhz!!

Which one would have the advantage in SLI configurations, or games in general... a faster DDR rate, or a wider bus?

 

[Rys]

Assuming peak bandwidth utilisation in both cases, and sensible clocks and widths, it wouldn't really matter either way.

 

[leoneazzurro]

http://www.overclockers.ru/hardnews/28879.shtml
They say: GT200 is a monster...
10 clusters with 24 "SPs" and 8 TMUs -> 240 SPs and 80 TMUs at all
512bit MI with GDDR3
32 ROPs,
Some kind of CFAA, possible D3D10.1

Seems a little too big for a "around 1 Billion transistors" chip.
I'd bet for 192 SP and regarding the 32 ROPS... they seem a little too much, either.
But if it's a 1.5 Billion transistors, it may be.

 

[AnarchX]

GT-200 is supposed to be around 600mm^2, so it should be of course over 1 billion transistors.

 

[DegustatoR]

Seems a little too big for a "around 1 Billion transistors" chip.
I'd bet for 192 SP and regarding the 32 ROPS... they seem a little too much, either.
But if it's a 1.5 Billion transistors, it may be.

10 SP clusters is a given and you can't have 192 SPs in 10 clusters.
So it's either 240 (24 SPs per cluster) or 160 (16 SPs per cluster).
Although i agree that "around 1 bln transistors" is a bit small for such chip.

 

[leoneazzurro]

GT-200 is supposed to be around 600mm^2, so it should be of course over 1 billion transistors.

I mean: "around 1 Billion" is different from "around 1.5 billions". And with the rumored (but unconfirmed) 600 mm^2 at 65 nm it would be closer to 1.5 than 1.0 Billion transistors. At 55 nm it would be more than 1.5 Billion transistors.

"Around 1 Billion transistors" IMHO copes better with a 192 "SP" variant than with a 240 "SP" one.

 

[leoneazzurro]

10 SP clusters is a given and you can't have 192 SPs in 10 clusters.
So it's either 240 (24 SPs per cluster) or 160 (16 SPs per cluster).
Although i agree that "around 1 bln transistors" is a bit small for such chip.

Sorry, I'm missing the official news where GT200 it is said to have 10 clusters.

Aside from jokes, I was not really commenting the russian site rumor itself, I was merely referring to the supposed number of transistors for GT 200 related to the "SP" and ROPs numbers and gave my opinion about what I expect the GT200 will be.
To expect to have 2x the hardware resources of G92 (except for texturing, which should be "merely" 25% more), with 33% only more transistors (giving moreover a die size of 430 mm^2@65 nm or 310mm^2 @ 55nm instead of the rumored 600) seems a little out of reality: Happy to be wrong, however

 

[Mart]

1100Mhz GDDR3 (2200Mhz effective) gives 140.8GB/s on a 512bit bus.

Thats quite a bit higher than the Ultra with only 103.7GB/s.

Oops, for some reason I thought it would be 2100MHz effective

Still, 9800GTX has half that bandwidth, and seems to be limited on that front (The 9600GT, with only half the SPs, performs really well compared with it)
Wouldn't it be a mistake if NVIDIA were to (nearly) double the amount of ALUs (240), creating a huge chip that would in the end be limited by its bandwidth? Wouldn't that be a waste of die space?
If so, perhaps the 160 SP rumour has more credibility. Or perhaps the shader clocks could be significantly lower, for better thermal and power characteristics.

 

[AnarchX]

ALUs are normally not limited by BW.

Another point:
16 ROPs -> 32 ROPs
256-Bit -> 512-Bit
...

 

[nAo]

ALUs are normally not limited by BW.

I know at least a couple of GPU architectures that disagree with this statement.

 

[ShaidarHaran]

I know at least a couple of GPU architectures that disagree with this statement.

anything recent though?

 

[nAo]

anything recent though?

yep

 

[ShaidarHaran]

yep

such as...

 

[nAo]

such as...

I don't want to make nda ninjas cry

 

[ShaidarHaran]

I don't want to make nda ninjas cry

Oh, ok. So RV770 or GT200 then. Hmmm.......

 

[Voltron]

He also said they were working things that were miles ahead of the competition. Surely he must have meant being able to use CUDA to run those many parallel processors for good use in computational finance, medicine, weather, etc?

Though clearly the underpinnings of CUDA are very, very important to NVIDIA and I basically agree with your thoughts, it is unlikely that he was just referring to just this since the process of designing and bringing these things to the market is so complex. But obviously they have some interesting stuff going on to exploit their processors in the future.

One thing that I am curious about is CUDA and their internal design and architecture tools. These tools have always been a key part of NVIDIA's success, but it seems like it is only a matter of time before they can harness heterogeneous computing to make some big efficiency gains here.

 

[AlNom]

I know at least a couple of GPU architectures that disagree with this statement.

RSX Secret?

 

[AnarchX]

I know at least a couple of GPU architectures that disagree with this statement.

Sure, there could be some special cases, which I included with "normally".
But I do not think 240 MADD+MUL SPs could be limited by ~100GB/s, since in high arithmetical throughput scenarios most data should be stay in the GPU.

 

[trinibwoy]

Yeah I'm not seeing how GT200 will be equally or more bandwidth limited than G92. Assuming a 512-bit bus and 80 TMU's bandwidth doubles while texturing capability only increases by 25%.

However, you can probably make a case for the TMU's in G92 being bottlenecked by the shader array. In which case a significant increase in ALU capacity could increase demand for bandwidth indirectly by increasing TMU utilization.