Love_In_Rio said:2 times the G92 transistors and 1.5 times G92 performance is an efficiency increment ?
The 1.5x is referring to architectual improvements (a performance per unit per clock increase).
Love_In_Rio said:2 times the G92 transistors and 1.5 times G92 performance is an efficiency increment ?
no-X said:nVidias magicians work in marketing department and their misson is simple - to conceal weak points of the new GPU (which seems to be i bit older than G92/G94)
40 TAs instead of 80?So what specifically is wrong with texture adressing in these cards that puts them behind G9x cards... I need you to spell it out for me.
60.It's not 40 though.
You mean nVidia NDA'd people and then told them false info?It's not 40 though.
No, it's a dedicated unit. That's what I've been told.I would have thought it would have saved hardware if the DP unit shared hardware with the SP units.
At 1/12, it's almost like only one SIMD of 3 can run quarter-rate DP math.
How do you know it's not 40?
ATI uses four out of the five ALUs to perform a single-cycle double-precision MAD. It can do 2 independent ADDs per cycle, x,y lanes for one ADD, z,w lanes for the other.=>Jawed: How does ATi hardware handle double-precision computing? Through the same SPs that are used for single-precision, or are there some of them that support FP64 while others don't?
=>Jawed: How does ATi hardware handle double-precision computing? Through the same SPs that are used for single-precision, or are there some of them that support FP64 while others don't?
=>AnarchX: I don't have those. I just know what nVidia tols us under NDA weeks ago. SP count, TU count, memory bus and size, new features... since you're now saying that it was wrong, I see no problem in telling you, the TU count was supposed to be 40 (I thought 40 TAs + 80 TFs like on G80). So, nVidia did NDA people and told them false info. Feh!