Which is why I didn't chose Tukwila, but Dunnington. Yes it's expensive, but personally I don't think that's because they are running yields below the 5 procent ... not after an entire year in production.
NVIDIA Fermi: Architecture discussion
- Thread starter Rys
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So far rumored A3 is merely one re-spin since A2 is usually production silicon for NV. The very same rumors point at A3 supposedly not being a chip design fix, but you cannot of course trust them at this point.
Does it matter if Cypress and Juniper were originally slated to debut together for the given point? Or would it matter more that Hemlock appeared slightly later than Cypress? Yes of course are there differences in design philosophies, but I just can't buy that NV couldn't get a performance part faster out the door under the circumstances than a larger high end part. And yes of course if such a scenario is even possible it has to get planned a considerable time before the projected release targets.
NVIDIA's history certainly indicates that the high-end chip is the first to come out, but given that they are late to the show, I too have a hard time believing that they won't have a mid-range part at launch or just a couple of weeks after. The exact same one I've speculated before, with half everything that will be GF100.
A mid-range part would be a Juniper competitor; I'm rather pointing in the performance/Cypress competing solution direction.
I think Anand mentioned that the Juniper team couldn't do much until Cypress itself was presumably problem-free, and yet Juniper was still shown in June/July.
Probably 40nm capacity spacing and ramping up Juniper for OEMs/channel and such needing time. I still think they overestimated Juniper's sales potential, but they still have a few months, half a year perhaps, if nVidia's execution is any indication
Probably 40nm capacity spacing and ramping up Juniper for OEMs/channel and such needing time. I still think they overestimated Juniper's sales potential, but they still have a few months, half a year perhaps, if nVidia's execution is any indication
Yeah, I've talked about that too, in a post a few pages back. That would be the GeForce 360, which I speculated as a new chip with 384 SPs and not a cutdown version of the full Fermi chip (which I called GeForce 370, with 448 or 480 SPs).
Still, IMO NVIDIA is better off in releasing something in the mid-range too, where the big profits are.
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But if the performance chip is ready before the High-End and they could sell a dual GPU-Version of it, before the High-End-Single-Chip is available the market for that High-End-GPU would be smaller.
I do hope though that the performance chip will follow Fermi soon.
DegustatoR
Veteran
Fermi is an architecture not a chip.
Well I've heard this talk of Nvidia not following TSMC's guidelines on 40nm design from a few different sources now. If there's any truth to that it could be coming back to bite them in the ass so who know what they're scrambling to fix at this point.
Yep, it does matter because if Juniper was originally slated to debut a while after Cypress then it means AMD also gets their "big" chip perfected first before scaling down. Rumours place Cypress in Q2 so it could have simply been TSMC's delays that caused them to arrive together.
That's a fair assumption but it doesn't mean that leading with a performance part makes it easier to get the high-end stuff out faster. For example, if GF100 was only half of what it is - say just 8 cores - would it have been here by now or is there something else going on other than the fact it's a big chip? GT2xx derivatives are tiny aren't they and that didn't seem to help much at all.
The way this usual work is like this: the fab provides a deck with design rules. The fabless company does place and route and circuit design against those rules. Before tape-out, the fabless company does many DRC runs until the GDS2 file is clean against the design rule deck. When the fab receives the GDS2 file, it runs DRC on their site to, otherwise the tape out is rejected.
The one place where DRC violations are acceptable is for memories: the fab provides a basic 1-bit memory cell that can be used by a design house to build their own RAMs. Those cells violate the standard DRC deck, but are pre-approved by the fab.
All other DRC violations have to be explicitly signed off with the fab first, otherwise you're on your own.
Most companies won't bother because, other than RAM's, there's really not much to gain. It's possible that big boys do it for whatever reason, but it's not possible to sneak it past the fab.
Now that's specific for DRC only. There are many other parameters, of course. Circuit design is done against the approved spice deck of the fab. And much more fluid also. (The fab adjust parameters over time. Pretty much always making performance worse.) Noise calculations are ultimately also derived from that, but there are steps in between to simplify the Spice model into a still simplerer model etc.
Anyway: you heard multiple sources talking about Nvidia not following the rules. It's the first time I hear about this. (Actually, I've never heard any rumors about any company not following the rules.) Can you give some pointers?
trini and charlie might not have enough faith in each other, they've been hearing the same things everyone else has for the past half year. NV skimped on the 40nm design rules and that's causing huge leakage everywhere on the die, but especially the MC.
(Look in Charlie's articles which component is so messed up because of this we haven't seen anything faster than the GT215 in the past 1,5 years from NV.)
(no I'm not one of the sources)
I wasn't thinking of a possibility to get the high end part earlier out the door. I'm just thinking that a chip with smaller complexity might have had chances to get earlier released then GF100 in the foreseeable future. In the end the only other gain for NV in theory would be that the gap before AMD's first DX11 GPU release and NV's first DX11 GPU release could have been smaller.
As for the possibility of them having violated TSMC's 40nm rules I can't of course know if it's true or not. If yes you're absolutely right then and yes the GT21x@40nm would bear an example that would speak against any other theories.
Two things though:
1. Accepting the above would not explain AMD's 40nm supply problems.
2. A3 from what I've heard has been described as a quick respin with some process oriented fixes. A hypothetical violation of TSMC's 40G rules doesn't suggest in my mind anything "quick" nor "just a few fixes" either.
Yes of course are there also the indirect funky theories that some dark evil hand might be limiting AMD's supplies and albeit I like fairytales it doesn't mean that I also believe them
If A3 was a quick respin much like the GT200b3 was, wouldn't we had lot's of product showings, demo's and even pre-production products out?
b2 was in much the same position then and they ran with demoing that for 6 months before offering it for reviews.
If they truly went for a A3 re-spin, even the rumored CES hypothetical introduction sounds like a tough cookie to me.
As for GT200@55nm/B2 they were used in GTS260/216 SKUs if memory serves well.
Review samples yes, plenty. I think we still have to see end-user pics with b2's.
Is this supposed to be a variant of this?
Thanks for the insight. It's all hearsay with no evidence (per usual) so I'm not putting any stock in it yet, especially after your post.
Well yeah TSMC's own problems make it difficult to allocate blame. Who knows, maybe GT2xx was so late because Nvidia was unwilling to launch a high volume, low cost part until there was sufficient supply from TSMC. There are a lot of potential variables. And any problems that AMD saw are going to be magnified significantly for Nvidia given how much more ambitious Fermi is than Cypress.
In terms of the A3 spin do you really have any confidence in any Fermi rumours on either manufacturing status or timeline at this point? It seems to be shifting on a weekly basis.
This simple fact is that we have 4 products ramped/ramping on a (relatively) new, capacity constrained process in a market where demand is high for everything and our 40nm products are the only parts with the latest feature set.
