NVIDIA Fermi: Architecture discussion

[karlotta]

Hmmm the way back but its always the same.....ill just go to 2003
http://74.200.65.90/showpost.php?p=185938&postcount=28 The life of Brian,, or as the Fermi spins

 

[seahawk]

ATI has only a problem in the regard that TSMC is not giving them enough 40nm capacity, as NV blocks a lot with their sucking GT21X line.

And if you want to talk about the "M-Word" for Fermi better make it the other M-Word. Even Fraudo is losing faith in his master and it seems like dark thoughts are crossing his mind, like Fermi being a total disaster.

 

[MfA]

Meh, Intel has been making 500mm 45nm dies in volume for how long now? NVIDIA overestimated TSMC, but TSMC is performing far below realistic expectations at the moment.

 

[neliz]

And if you want to talk about the "M-Word" for Fermi better make it the other M-Word. Even Fraudo is losing faith in his master and it seems like dark thoughts are crossing his mind, like Fermi being a total disaster.

Yep. Q2 is now a far more realistic target.

 

[Razor1]

That the yields suddenly go down from where they are now perhaps? Fudo is horribly wrong about the yields, they are MUCH better for ATI than he is saying. I have some strong suspicions of what NV's are, internally described as "horiffic", and a much better idea of what ATI's are.

As I said here, ATI did their homework, and now have a good handle on the process, and how to work with it. NV was arrogant an tried to intimidate physics into doing what they wanted by yelling a lot. It didn't work.

I would bet that Fudo is parroting back NV FUD to try and deflect sales from ATI when the pipes start filling in a couple of weeks. Everything I hear says that article is complete bull.

Also, you should frame that argument in the context of NV blaming TSMC for all their woes lately. That saves them from having to take blame themselves, something that is against company rules, just like honesty.

-Charlie

Yeah when was the last time you heard that outside of your statements, sorry I've haven't been able to find out anytime when this has ever happened even outside of TSMC and your statements. Chuck, if you are amicable for me to call you that, if not let me know, yields just don't drop, some sizable explination, TSMC really scewed up with calibration of some of thier equipment, but still thats an easy problem to see , which you actually suggesting in not so choice of words to a certain vendor in one of your articles or should I say posts! Dude its not possible for that to just happen.

I think the 3rd rule is someone from NV PR must personally piss in your oatmeal every morning Or is this your subtle way of telling us you now work for NV and are all up speed and well practiced in official corporate policy?

its not piss its loose stools, it would mix well oatmeal and not be noticed till ya ate sorry for getting so graphic !

 

[itsmydamnation]

Meh, Intel has been making 500mm 45nm dies in volume for how long now? NVIDIA overestimated TSMC, but TSMC is performing far below realistic expectations at the moment.

what do intel make thats 500mm² ???? I7 is around 750million @ 263mm² and something like the Q9550 is only 850million with 12mb of Level cache @ 214mm²


both 45nm

 

[Mindfury]

what do intel make thats 500mm² ???? I7 is around 750million @ 263mm² and something like the Q9550 is only 850million with 12mb of Level cache @ 214mm²


both 45nm

Itanium

 

[Razor1]

Itanium

don't remember but I don't think it was 500nm2 even for itanium 2.

 

[itsmydamnation]

don't remember but I don't think it was 500nm2 even for itanium 2.

592,000,000 transistors at 130nm so yes, big, but hardly relevent to 45/32nm era.

 

[MfA]

Dunnington ... now of course they have oodles of cache, but GPUs can have redundancy in their logic to a far greater extent than CPU cores, so meh.

PS. they can have redundancy to a far greater extent, to what extent NVIDIA made use of that is of course one big question mark ... they might just have too much non redundant circuitry.

 

[silent_guy]

NV was arrogant an tried to intimidate physics into doing what they wanted by yelling a lot. It didn't work.

It's a funny sound bite, alright.
It also doesn't make any sense.

 

[trinibwoy]

I would bet that Fudo is parroting back NV FUD to try and deflect sales from ATI when the pipes start filling in a couple of weeks. Everything I hear says that article is complete bull.

FUD or not, claims of ATI having low yields certainly isn't affecting demand now and won't in the future either. Why would customers give a hoot about yields if there's product on the shelves?

Also, you should frame that argument in the context of NV blaming TSMC for all their woes lately. That saves them from having to take blame themselves, something that is against company rules, just like honesty.

That's neither here nor there. Blaming TSMC won't make Fermi appear (ooh that rhymes ).

 

[Ailuros]

So Lara Bee it is.

-Charlie

Less than semi accurate

Well that sorta assumes its trivial to make a small chip and then make a bigger chip based on the same design. Not even the CPU guys do that. So even if they were to get the smaller chip out faster it might take them that much longer to do the bigger variant. Of course, this is based on an assumption that scaling up a design is harder than scaling it down.

Much longer than what for the high end part? Longer than today? Chances are high that when they finally release GF100 the smaller members of the family will quickly follow behind it or else due to the delay of GF100 the intermediate time before high end and lower end SKUs release timings must have shrunk considerably. Meaning if my notion makes any sense it has nothing to do with scaling up in the least, just a slight change in manufacturing priorities.

 

[mczak]

Dunnington ... now of course they have oodles of cache, but GPUs can have redundancy in their logic to a far greater extent than CPU cores, so meh.

Dunnington is indeed 500mm². And for high-end chips, that's certainly not an unusual size, all Itaniums were around that or bigger. Tukwila is said to be 700mm², but this thing is so late it's still on 65nm and not out yet so maybe that's not a good reference point for demonstrating how easy it is to produce large chips... Certainly Nehalem-EX (Beckton) and IBM's Power7 will also have similar die sizes (both at 45nm) but neither one is out yet. Besides, these chips cost way more than any complete graphic card (except the professional variants) so yields probably wouldn't be that much of an issue even if low.

 

[thatdude90210]

That's neither here nor there. Blaming TSMC won't make Fermi appear (ooh that rhymes ).

No, but it helps to present their own engineering team as less incompetent to shareholders. Nobody can get any .40 parts out of TSMC.

 

[trinibwoy]

Much longer than what for the high end part? Longer than today? Chances are high that when they finally release GF100 the smaller members of the family will quickly follow behind it or else due to the delay of GF100 the intermediate time before high end and lower end SKUs release timings must have shrunk considerably. Meaning if my notion makes any sense it has nothing to do with scaling up in the least, just a slight change in manufacturing priorities.

It only works out that way if the delay is due to external circumstances. Do we know that Cypress and Juniper were originally slated to debut together?

However, if there's something inherently wrong with the design that is causing the delay then you can't really expect to have derivatives out shortly afterward. It very much looks like Nvidia is facing this scenario with the multiple rumoured respins.

No, but it helps to present their own engineering team as less incompetent to shareholders. Nobody can get any .40 parts out of TSMC.

Most shareholders aren't going to try to guess the future based on internet gossip and Charlie's rants. There's a big disconnect between what enthusiasts think matters and what really does. For example, in spite of all the renaming broohaha it looks like G92 is still doing fine.

 

[Groo The Wanderer]

I think the 3rd rule is someone from NV PR must personally piss in your oatmeal every morning Or is this your subtle way of telling us you now work for NV and are all up speed and well practiced in official corporate policy?

No, just that in several years of working with them, they have never told the truth, they always spin a response in some way at the bare minimum, and outright lies are not uncommon. Since the new PR guys took over, it has gotten much worse, I am not sure where they dredged this crew up from (actually, it was HP, if you want an ear full, call there and ask....), but they take things a step further in the wrong direction.

I have honestly never worked with a company that is as dishonest as Nvidia. ATI under Evendon (now at NV FWIW) bent things to the breaking point, but never outright lied. Intel only goes as far as selective quoting and other similar things, and AMD AMD is pretty above board all the time as well. 'New ATI' is much closer to AMD than anything else.

Smaller companies are all over the map, but none even come close to NV's level of sleaze. There is a spectrum of good and bad, and then there is NV off to one side, WAY off. It is really impressive how they manage to be dishonest with the press even when it is detrimental to their own goals. I really don't get it.

That said, they are impossible to work with.

I have two rules that I keep telling them, and that they keep ignoring. I will not consider them safe to work with unless they follow those two rules. They are:
1) Don't lie to me
2) Don't play petty power games with me
That's it. I tell them that repeatedly, have been for years. Nothing has changed on my end, but their end got worse.

The new regime there botched the first opportunity they got. See here, and read the notes for more. Epic fail from a bunch of second rate chuckleheads. Then again, if NV wanted something more than a sock puppet this time around, they would have hired one. They didn't.

They never admit anything is their fault, it is always a partner, someone who misunderstands, or someone who is out to get them. They have not even admitted that bumpgate is their fault, it is TSMC, packaging houses, stupid users, incompetent OEMs, and everyone else.

Simply put, the company, every person there that I have dealt with, is in my opinion, simply dishonest. Are there good people there? Possibly, even likely. No, I know a few that are 'not allowed' to talk to me, but that is about it.

Ah well, they know what it will take to patch things over, but refuse to attempt it. Not my problem any more, the worse they get, the funnier it is for me. "This puppy is Fermi". Pure comedy gold, keep it coming guys.

-Charlie

 

[Groo The Wanderer]

Yeah when was the last time you heard that outside of your statements, sorry I've haven't been able to find out anytime when this has ever happened even outside of TSMC and your statements. Chuck, if you are amicable for me to call you that, if not let me know, yields just don't drop, some sizable explination, TSMC really scewed up with calibration of some of thier equipment, but still thats an easy problem to see , which you actually suggesting in not so choice of words to a certain vendor in one of your articles or should I say posts! Dude its not possible for that to just happen.

Sure, call me anything you want, words don't bother me.

That said, the chamber mismatch is a bring up error, it should not have affected tools in production, nor should it have been missed by metrology in a running system. TSMC is bringing up a second 40nm line now, and that is likely where things went awry for the mismatch.

Unfortunately, that does not explain the yield drop on the existing line, but that has been taken care of. It was a hiccup, but a very interestingly timed one.

I am not sure the last bit of your statement parses correctly in english, so if you would care to clarify, I will try and answer it.

-Charlie

 

[digitalwanderer]

Unfortunately, that does not explain the yield drop on the existing line, but that has been taken care of. It was a hiccup, but a very interestingly timed one.

How do we know it has been taken care of if we don't know what it was? :|

 

[Razor1]

Sure, call me anything you want, words don't bother me.

That said, the chamber mismatch is a bring up error, it should not have affected tools in production, nor should it have been missed by metrology in a running system. TSMC is bringing up a second 40nm line now, and that is likely where things went awry for the mismatch.

Unfortunately, that does not explain the yield drop on the existing line, but that has been taken care of. It was a hiccup, but a very interestingly timed one.

I am not sure the last bit of your statement parses correctly in english, so if you would care to clarify, I will try and answer it.

-Charlie

TSMC will not sabotage themselves.


That is what I am saying the chamber mismatch in the new line would not effect the first line, what does that mean, pretty simple yields were a problem on that line too.