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We could see another RT core Iteration.. . Who knows! But Yeah, That sounds realistic
I hope it doesn't take that long to come out. There's speculation in the RDNA3 thread of RDNA 3 landing by end of Q1 next year.
That would be the 3rd iteration then, one could hope they would start going for L3 RT.
RedGamingTech said that he heard that Lovelace isn't consumer, overall the near future could just be "Ampere Next" for next year and then "Ampere Next Next".
I think a AD102/GA202 could have a 384-bit bus with a 192 MB cache, not sure if GDDR6X (hopefully not after the hot and hungry SKUs it's with) or GDDR7 (doable if Computex the earliest) at 24Gbps, would be able to feed the 2-2.3x rumors we have about the top RTX 40 SKUs. Overall I think the RTX 40 lineup could look like this:
AD102/GA202 SKUs
RTX Titan II:
o 144 SMs.
o 384 Bit Bus.
o 48 GB of GDDR*
o 2000-2500 USD
RTX 4090:
o 140 SMs.
o 384 Bit Bus.
o 24 GB of GDDR
o 1200 USD
RTX 4080:
o 116 SMs.
o 384 Bit Bus.
o 20 GB of GDDR (slower than 4090/Titan 2)**
o 800 USD
AD104/GA204 SKUs
RTX 4070:
o 82 SMs.
o 257 Bit Bus.
o 16 GB of GDDR
o 600 USD
RTX 4060:
o 64 SMs.
o 224 Bit Bus.
o 14 GB of GDDR (slower than 4070)**
o 450 USD
AD106/GA206 SKUs
RTX 4050:
o 46 SMs.
o 192 Bit Bus.
o 12 GB of GDDR
o 350 USD
RTX 4040:
o 34 SMs.
o 160 Bit Bus.
o 10 GB of GDDR (slower than 4050)**
o 250 USD
*RTX Titan II would be using double sided memory ala 3090, but I think Nvidia will want to bring back the Titan as the prosumer they can jack up the cost to whatever they want.
**4080/4060/4040 would have slower memory as it makes it easier for Nvidia to segment the line up in terms of performance and space SKUs. No Tis as Nvidia originally wanted for RTX 30 but AMD forced their hand.
TopSpoiler
Regular
MCM or monolithic?
Almost everyone says monolithic, big question is if say a RTX 4090 can hit 2.2x over a 3090 and so on.
Assume SEC 4LPP which is very close to TSMC 5P (much more competitive than previous round SEC 8nm vs TSMC 7nm)
But some rumors say TSMC N5 is the choice for RTX 40 since SEC's processes aren't yielding well.
https://en.wikipedia.org/wiki/Ada_Lovelace
Regarded as one of the first if not the first computer programmers. Daugther of poet Lord Byron. They both died untimely at age 36.
Regarded as one of the first if not the first computer programmers. Daugther of poet Lord Byron. They both died untimely at age 36.
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The three options Nvidia has for bandwidth are: HBM (expensive). Go back to GDDR6, which is now as fast as GDDR6x, and implement a 512bit bus. And go with a big LLC like AMD has done.
None of them are ideal of course; a 512bit bus has its own costs; as does a big LLC as we can see from RDNA2 having a deficit in deferred titles at high resolutions (wonder what effect a visibility buffer has on that). Regardless, for performance increases they're also heavily constrained by power. Even jumping from Samsung 8nm to TSMC 5nm there isn't enough power savings to double performance, so unless there's a major architecture shift simultaneously that notion is out.
As a guess, lower end of expectations is a switch to a big LLC and a 25% performance improvement (averaged) with a switch to GDDR6 to save money. But better is always possible.
None of them are ideal of course; a 512bit bus has its own costs; as does a big LLC as we can see from RDNA2 having a deficit in deferred titles at high resolutions (wonder what effect a visibility buffer has on that). Regardless, for performance increases they're also heavily constrained by power. Even jumping from Samsung 8nm to TSMC 5nm there isn't enough power savings to double performance, so unless there's a major architecture shift simultaneously that notion is out.
As a guess, lower end of expectations is a switch to a big LLC and a 25% performance improvement (averaged) with a switch to GDDR6 to save money. But better is always possible.
D
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Obviously this isn't coming to Lovelace, but with PCIe 6.0 bringing 128GB/s duplex (256GB/s raw) and DDR5 hitting ~100GB/s in a 2-module configuration, I wonder if we'll start seeing DRAM-less midrange GPUs that only bring large amounts of stacked LLC.
Jawed
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D
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I think it's just a suggested prefix that uses "Ada" as acronym.
Wouldn't that make the GPU performance too much dependent on the rest of the system? Sounds like a PR nightmare.
D
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Is it that much different to being able to pair a RTX3090 with a 2-core/2-thread Celeron using the motherboard's chipset-driven PCIe 3.0 x4 slot that is usually full sized?
Or pairing a 5700G APU with just one module of DDR4-1600?
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